litedram/litedram
Florent Kermarrec 8d39ac6dd1 phy/s7ddrphy: remove interface_type parameter and ISERDESE2's MEMORY_MODE support.
Supporting MEMORY_MODE add complexity to the codebase and this mode is not used by anyone.
It has been experimented on NeTV2 to solves instability at low temperature but hasn't improved
the behaviour.
2020-09-15 19:55:58 +02:00
..
core core/multiplexer/steerel_sel: add support for dynamic rd/rdcmd/wr/wrcmd phases. 2020-09-14 18:40:58 +02:00
frontend add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
phy phy/s7ddrphy: remove interface_type parameter and ISERDESE2's MEMORY_MODE support. 2020-09-15 19:55:58 +02:00
__init__.py update code, start bankmachine refactoring and remove old code (will be rewritten) 2015-09-15 10:22:39 +02:00
common.py s7ddrphy/usddrphy: add cmd_delay parameter and pass cmd_latency/cmd_delay to PhySettings/Software. 2020-09-07 18:50:01 +02:00
dfii.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
gen.py litedram/gen: update LiteDRAMECP5DDRPHYCRG (AsyncResetSynchronizer integrated in PLL). 2020-09-01 13:58:16 +02:00
init.py phy/s7ddrphy: reduce BitSlip's cycles to 1 (seems to be enough for all cases). 2020-09-15 19:50:45 +02:00
modules.py modules: remove unnecessary memtypes. 2020-09-01 13:43:09 +02:00