209 lines
7.8 KiB
Python
209 lines
7.8 KiB
Python
#
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# This file is part of LiteDRAM.
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#
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# Copyright (c) 2021 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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import itertools
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from migen import *
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from litedram.phy.utils import Serializer, Deserializer, Latency, chunks, bit
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from litex.gen.sim import run_simulation as _run_simulation
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def run_simulation(dut, generators, clocks, debug_clocks=False, **kwargs):
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"""Wrapper that can be used to easily debug clock configuration"""
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if debug_clocks:
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class DUT(Module):
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def __init__(self, dut):
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self.submodules.dut = dut
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for clk in clocks:
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setattr(self.clock_domains, "cd_{}".format(clk), ClockDomain(clk))
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cd = getattr(self, 'cd_{}'.format(clk))
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self.comb += cd.rst.eq(0)
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s = Signal(4, name='dbg_{}'.format(clk))
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sd = getattr(self.sync, clk)
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sd += s.eq(s + 1)
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dut = DUT(dut)
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_run_simulation(dut, generators, clocks, **kwargs)
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class TestSimSerializers(unittest.TestCase):
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def run_simulation(self, dut, generators, **kwargs):
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clocks = {
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"sys": (64, 31),
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"sys_11_25": (64, 29), # aligned to sys8x_90 (phase shift of 11.25)
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"sys2x": (32, 15),
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"sys8x": ( 8, 3),
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"sys8x_ddr": ( 4, 1),
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"sys8x_90": ( 8, 1),
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"sys8x_90_ddr": ( 4, 3),
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}
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run_simulation(dut, generators, clocks, **kwargs)
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@staticmethod
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def data_generator(i, datas):
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for data in datas:
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yield i.eq(data)
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yield
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yield i.eq(0)
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yield
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@staticmethod
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def data_checker(o, datas, n, latency, yield1=False):
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if yield1:
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yield
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for _ in range(latency):
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yield
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for _ in range(n):
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datas.append((yield o))
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yield
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yield
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def serializer_test(self, *, data_width, datas, clk, clkdiv, latency, clkgen=None, clkcheck=None, **kwargs):
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clkgen = clkgen if clkgen is not None else clkdiv
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clkcheck = clkcheck if clkcheck is not None else clk
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received = []
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dut = Serializer(clk=clk, clkdiv=clkdiv, i_dw=data_width, o_dw=1)
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generators = {
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clkgen: self.data_generator(dut.i, datas),
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clkcheck: self.data_checker(dut.o, received, n=len(datas) * data_width, latency=latency * data_width, yield1=True),
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}
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self.run_simulation(dut, generators, **kwargs)
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received = list(chunks(received, data_width))
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datas = [[bit(i, d) for i in range(data_width)] for d in datas]
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self.assertEqual(received, datas)
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def deserializer_test(self, *, data_width, datas, clk, clkdiv, latency, clkgen=None, clkcheck=None, **kwargs):
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clkgen = clkgen if clkgen is not None else clk
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clkcheck = clkcheck if clkcheck is not None else clkdiv
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datas = [[bit(i, d) for i in range(data_width)] for d in datas]
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received = []
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dut = Deserializer(clk=clk, clkdiv=clkdiv, i_dw=1, o_dw=data_width)
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generators = {
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clkgen: self.data_generator(dut.i, itertools.chain(*datas)),
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clkcheck: self.data_checker(dut.o, received, n=len(datas), latency=latency),
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}
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self.run_simulation(dut, generators, **kwargs)
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received = [[bit(i, d) for i in range(data_width)] for d in received]
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self.assertEqual(received, datas)
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DATA_8 = [0b11001100, 0b11001100, 0b00110011, 0b00110011, 0b10101010]
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DATA_16 = [0b1100110011001100, 0b0011001100110011, 0b0101010101010101]
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ARGS_8 = dict(
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data_width = 8,
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datas = DATA_8,
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clkdiv = "sys",
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clk = "sys8x",
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latency = Serializer.LATENCY,
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)
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ARGS_16 = dict(
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data_width = 16,
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datas = DATA_16,
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clkdiv = "sys",
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clk = "sys8x_ddr",
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latency = Serializer.LATENCY,
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)
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def _s(default, **kwargs):
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def test(self):
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new = default.copy()
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new.update(kwargs)
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self.serializer_test(**new)
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return test
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def _d(default, **kwargs):
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def test(self):
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new = default.copy()
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new["latency"] = Deserializer.LATENCY
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new.update(kwargs)
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self.deserializer_test(**new)
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return test
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test_sim_serializer_8 = _s(ARGS_8)
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test_sim_serializer_8_phase90 = _s(ARGS_8, clkdiv="sys_11_25", clk="sys8x_90")
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# when clkgen and clkdiv are not phase aligned (clkdiv is delayed), there will be lower latency
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test_sim_serializer_8_phase90_gen0 = _s(ARGS_8, clkdiv="sys_11_25", clk="sys8x_90", clkgen="sys", latency=Serializer.LATENCY - 1)
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test_sim_serializer_8_phase90_check0 = _s(ARGS_8, clkdiv="sys_11_25", clk="sys8x_90", clkcheck="sys8x")
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test_sim_serializer_16 = _s(ARGS_16)
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test_sim_serializer_16_phase90 = _s(ARGS_16, clkdiv="sys_11_25", clk="sys8x_90_ddr")
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test_sim_serializer_16_phase90_gen0 = _s(ARGS_16, clkdiv="sys_11_25", clk="sys8x_90_ddr", clkgen="sys", latency=Serializer.LATENCY - 1)
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test_sim_serializer_16_phase90_check0 = _s(ARGS_16, clkdiv="sys_11_25", clk="sys8x_90_ddr", clkcheck="sys8x_ddr")
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# for phase aligned clocks the latency will be bigger (preferably avoid phase aligned reading?)
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test_sim_deserializer_8 = _d(ARGS_8, latency=Deserializer.LATENCY + 1)
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test_sim_deserializer_8_check90 = _d(ARGS_8, clkcheck="sys_11_25")
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test_sim_deserializer_8_gen90_check90 = _d(ARGS_8, clkcheck="sys_11_25", clkgen="sys8x_90")
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test_sim_deserializer_8_phase90 = _d(ARGS_8, clkdiv="sys_11_25", clk="sys8x_90", latency=Deserializer.LATENCY + 1)
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test_sim_deserializer_8_phase90_check0 = _d(ARGS_8, clkdiv="sys_11_25", clk="sys8x_90", clkcheck="sys", latency=Deserializer.LATENCY + 1)
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test_sim_deserializer_16 = _d(ARGS_16, latency=Deserializer.LATENCY + 1)
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test_sim_deserializer_16_check90 = _d(ARGS_16, clkcheck="sys_11_25")
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test_sim_deserializer_16_gen90_check90 = _d(ARGS_16, clkcheck="sys_11_25", clkgen="sys8x_90_ddr")
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test_sim_deserializer_16_phase90 = _d(ARGS_16, clkdiv="sys_11_25", clk="sys8x_90_ddr", latency=Deserializer.LATENCY + 1)
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test_sim_deserializer_16_phase90_check0 = _d(ARGS_16, clkdiv="sys_11_25", clk="sys8x_90_ddr", clkcheck="sys", latency=Deserializer.LATENCY + 1)
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class LatencyTests(unittest.TestCase):
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def test_latency_default_zero(self):
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l = Latency()
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self.assertEqual((l._sys.numerator, l._sys.denominator), (0, 1))
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def test_latency_sys_init(self):
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for n in [0, 1, 2, 4, 9]:
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l = Latency(sys=n)
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self.assertEqual((l._sys.numerator, l._sys.denominator), (n, 1))
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def test_latency_get_sys(self):
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l = Latency()
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self.assertEqual(l.sys, 0)
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for n in [0, 1, 2, 4, 9]:
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l = Latency(sys=n)
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self.assertEqual(l.sys, n)
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def test_latency_get_sysNx(self):
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l = Latency()
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self.assertEqual(l.sys2x, 0)
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for n in [0, 1, 2, 4, 9]:
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l = Latency(sys=n)
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self.assertEqual(l.sys2x, 2*n)
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self.assertEqual(l.sys3x, 3*n)
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def test_latency_set_sysNx(self):
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for n in [3, 6, 9]:
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l = Latency(sys3x=n)
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self.assertEqual(l.sys, n // 3)
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def test_latency_add(self):
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l = Latency(sys=2) + Latency(sys2x=3)
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self.assertEqual(l.sys2x, 4+3)
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l = Latency(sys2x=2, sys4x=3) + Latency(sys4x=1)
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self.assertEqual(l.sys4x, 8)
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self.assertEqual(l.sys2x, 4)
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self.assertEqual(l.sys, 2)
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def test_latency_error_on_get_fraction(self):
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l = Latency(sys=1, sys2x=1)
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with self.assertRaises(ValueError):
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l.sys # would have to be 1.5
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l = Latency(sys3x=1, sys2x=1)
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for attr in "sys sys2x sys3x sys4x sys5x".split():
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with self.assertRaises(ValueError):
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getattr(l, attr)
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l.sys6x # ok
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