103 lines
3.6 KiB
Plaintext
103 lines
3.6 KiB
Plaintext
__ _ __ ___ ___ ___ __ ___
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/ / (_) /____ / _ \/ _ \/ _ | / |/ /
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/ /__/ / __/ -_) // / , _/ __ |/ /|_/ /
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/____/_/\__/\__/____/_/|_/_/ |_/_/ /_/
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Copyright 2015-2017 / EnjoyDigital
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A small footprint and configurable DRAM core
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[> Intro
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--------
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LiteDRAM provides a small footprint and configurable DRAM core.
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LiteDRAM is part of LiteX libraries whose aims are to lower entry level of
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complex FPGA cores by providing simple, elegant and efficient implementations
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ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
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The core uses simple and specific streaming buses and will provides in the future
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adapters to use standardized AXI or Avalon-ST streaming buses.
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Since Python is used to describe the HDL, the core is highly and easily
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configurable.
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LiteDRAM uses technologies developed in partnership with M-Labs Ltd:
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- Migen enables generating HDL with Python in an efficient way.
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- MiSoC provides the basic blocks to build a powerful and small footprint SoC.
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LiteDRAM can be used as a Migen/MiSoC library (by simply installing it
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with the provided setup.py) or can be integrated with your standard design flow
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by generating the verilog rtl that you will use as a standard core.
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[> Features
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-----------
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PHY:
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- Generic SDRAM PHY (vendor agnostic, tested on Xilinx, Altera, Lattice)
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- Spartan6 DDR/LPDDR/DDR2/DDR3 PHY (1:2 or 1:4 frequency ratio)
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- Kintex7 DDR3 PHY (1:4 frequency ratio)
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- Artix7 DDR3 PHY (1:4 frequency ratio)
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Core:
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- Fully pipelined, high performance.
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- Configurable commands depth on bankmachines.
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Frontend:
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- Configurable crossbar (simply declare your crossbar and use crossbar.get_port() to add a new port!)
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- Ports arbitration transparent to the user.
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- Wishbone bridge.
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- DMA reader/writer.
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- BIST.
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[> Possible improvements
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------------------------
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- add standardized interfaces (AXI, Avalon-ST)
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- add support for Altera PHYs.
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- add support for Lattice PHYs.
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- ... See below Support and consulting :)
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If you want to support these features, please contact us at florent [AT]
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enjoy-digital.fr. You can also contact our partner on the public mailing list
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devel [AT] lists.m-labs.hk.
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> Getting started
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------------------
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1. Install Python3 and your vendor's software
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2. Obtain LiteX and install it:
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git clone https://github.com/enjoy-digital/litex --recursive
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cd litex
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python3 setup.py install
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cd ..
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3. TODO: add example design(s)
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[> License
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----------
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LiteDRAM is released under the very permissive two-clause BSD license. Under
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the terms of this license, you are authorized to use LiteDRAM for closed-source
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proprietary designs.
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Even though we do not require you to do so, those things are awesome, so please
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do them if possible:
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- tell us that you are using LiteDRAM
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- cite LiteDRAM in publications related to research it has helped
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- send us feedback and suggestions for improvements
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- send us bug reports when something goes wrong
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- send us the modifications and improvements you have done to LiteDRAM.
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[> Support and consulting
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-------------------------
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We love open-source hardware and like sharing our designs with others.
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LiteDRAM is developed and maintained by EnjoyDigital. Initial development
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is based on MiSoC's LASMICON.
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If you would like to know more about LiteDRAM or if you are already a happy
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user and would like to extend it for your needs, EnjoyDigital can provide standard
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commercial support as well as consulting services.
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So feel free to contact us, we'd love to work with you! (and eventually shorten
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the list of the possible improvements :)
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[> Contact
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E-mail: florent [AT] enjoy-digital.fr |