155 lines
6.3 KiB
Python
Executable File
155 lines
6.3 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import argparse
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from migen import *
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from migen.genlib.misc import WaitTimer
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from litex.build.sim.config import SimConfig
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.tools.litex_sim import SimSoC
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from litedram.frontend.bist import _LiteDRAMBISTGenerator
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from litedram.frontend.bist import _LiteDRAMBISTChecker
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# LiteDRAM Benchmark SoC ---------------------------------------------------------------------------
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class LiteDRAMBenchmarkSoC(SimSoC):
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def __init__(self,
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sdram_module = "MT48LC16M16",
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sdram_data_width = 32,
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bist_base = 0x00000000,
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bist_length = 1024,
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bist_random = False,
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**kwargs):
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# SimSoC -----------------------------------------------------------------------------------
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SimSoC.__init__(self,
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with_sdram = True,
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sdram_module = sdram_module,
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sdram_data_width = sdram_data_width,
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**kwargs
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)
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# BIST Generator ---------------------------------------------------------------------------
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bist_generator = _LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
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self.submodules.bist_generator = bist_generator
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# BIST Checker -----------------------------------------------------------------------------
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bist_checker = _LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
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self.submodules.bist_checker = bist_checker
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# Sequencer --------------------------------------------------------------------------------
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class LiteDRAMCoreControl(Module, AutoCSR):
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def __init__(self):
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self.init_done = CSRStorage()
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self.init_error = CSRStorage()
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self.submodules.ddrctrl = ddrctrl = LiteDRAMCoreControl()
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self.add_csr("ddrctrl")
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display = Signal()
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finish = Signal()
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self.submodules.fsm = fsm = FSM(reset_state="WAIT-INIT")
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fsm.act("WAIT-INIT",
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If(self.ddrctrl.init_done.storage, # Written by CPU when initialization is done
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NextState("BIST-GENERATOR")
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)
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)
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fsm.act("BIST-GENERATOR",
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bist_generator.start.eq(1),
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bist_generator.base.eq(bist_base),
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bist_generator.length.eq(bist_length),
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bist_generator.random.eq(bist_random),
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If(bist_generator.done,
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NextState("BIST-CHECKER")
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)
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)
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fsm.act("BIST-CHECKER",
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bist_checker.start.eq(1),
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bist_checker.base.eq(bist_base),
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bist_checker.length.eq(bist_length),
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bist_checker.random.eq(bist_random),
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If(bist_checker.done,
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NextState("DISPLAY")
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)
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)
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fsm.act("DISPLAY",
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display.eq(1),
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NextState("FINISH")
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)
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fsm.act("FINISH",
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finish.eq(1)
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)
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# Simulation Results -----------------------------------------------------------------------
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self.sync += [
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If(display,
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Display("BIST-GENERATOR ticks: %08d", bist_generator.ticks),
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Display("BIST-CHECKER errors: %08d", bist_checker.errors),
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Display("BIST-CHECKER ticks: %08d", bist_checker.ticks),
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)
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]
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# Simulation End ---------------------------------------------------------------------------
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end_timer = WaitTimer(2**16)
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self.submodules += end_timer
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self.comb += end_timer.wait.eq(finish)
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self.sync += If(end_timer.done, Finish())
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteDRAM Benchmark SoC Simulation")
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builder_args(parser)
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soc_sdram_args(parser)
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parser.add_argument("--threads", default=1, help="Set number of threads (default=1)")
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parser.add_argument("--sdram-module", default="MT48LC16M16", help="Select SDRAM chip")
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parser.add_argument("--sdram-data-width", default=32, help="Set SDRAM chip data width")
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parser.add_argument("--trace", action="store_true", help="Enable VCD tracing")
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parser.add_argument("--trace-start", default=0, help="Cycle to start VCD tracing")
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parser.add_argument("--trace-end", default=-1, help="Cycle to end VCD tracing")
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parser.add_argument("--opt-level", default="O0", help="Compilation optimization level")
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parser.add_argument("--bist-base", default="0x00000000", help="Base address of the test (default=0)")
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parser.add_argument("--bist-length", default="1024", help="Length of the test (default=1024)")
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parser.add_argument("--bist-random", action="store_true", help="Use random data during the test")
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args = parser.parse_args()
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soc_kwargs = soc_sdram_argdict(args)
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builder_kwargs = builder_argdict(args)
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sim_config = SimConfig(default_clk="sys_clk")
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sim_config.add_module("serial2console", "serial")
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# Configuration --------------------------------------------------------------------------------
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soc_kwargs["sdram_module"] = args.sdram_module
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soc_kwargs["sdram_data_width"] = int(args.sdram_data_width)
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soc_kwargs["bist_base"] = int(args.bist_base, 0)
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soc_kwargs["bist_length"] = int(args.bist_length, 0)
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soc_kwargs["bist_random"] = args.bist_random
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# SoC ------------------------------------------------------------------------------------------
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soc = LiteDRAMBenchmarkSoC(**soc_kwargs)
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# Build/Run ------------------------------------------------------------------------------------
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builder_kwargs["csr_csv"] = "csr.csv"
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builder = Builder(soc, **builder_kwargs)
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vns = builder.build(
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threads = args.threads,
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sim_config = sim_config,
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opt_level = args.opt_level,
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trace = args.trace,
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trace_start = int(args.trace_start),
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trace_end = int(args.trace_end)
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)
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if __name__ == "__main__":
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main()
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