55 lines
1.9 KiB
Python
55 lines
1.9 KiB
Python
# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import unittest
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from migen import *
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from litex.gen.sim import run_simulation
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from litex.soc.interconnect import wishbone
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from litedram.frontend.wishbone import LiteDRAMWishbone2Native
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from litedram.common import LiteDRAMNativePort
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from test.common import DRAMMemory, seed_to_data
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class TestWishbone(unittest.TestCase):
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def test_wishbone_data_width_not_smaller(self):
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with self.assertRaises(AssertionError):
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wb = wishbone.Interface(data_width=32)
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port = LiteDRAMNativePort("both", address_width=32, data_width=wb.data_width * 2)
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LiteDRAMWishbone2Native(wb, port)
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def wishbone_readback_test(self, pattern, wishbone, port, mem_depth=64, **kwargs):
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class DUT(Module):
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def __init__(self):
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self.port = port
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self.wb = wishbone
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self.submodules += LiteDRAMWishbone2Native(self.wb, self.port, **kwargs)
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self.mem = DRAMMemory(port.data_width, mem_depth)
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def main_generator(dut):
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for adr, data in pattern:
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yield from dut.wb.write(adr, data)
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data_r = (yield from dut.wb.read(adr))
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self.assertEqual(data_r, data)
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dut = DUT()
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generators = [
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main_generator(dut),
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dut.mem.write_handler(dut.port),
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dut.mem.read_handler(dut.port),
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]
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run_simulation(dut, generators)
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mem_expected = [0] * mem_depth
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for adr, data in pattern:
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mem_expected[adr] = data
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self.assertEqual(dut.mem.mem, mem_expected)
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def test_wishbone(self):
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pattern = [(adr, seed_to_data(adr, nbits=32)) for adr in range(16)]
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wb = wishbone.Interface(data_width=32, adr_width=30)
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port = LiteDRAMNativePort("both", address_width=30, data_width=32)
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self.wishbone_readback_test(pattern, wb, port)
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