507 lines
17 KiB
Python
507 lines
17 KiB
Python
# This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
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# This file is Copyright (c) 2013-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2017 whitequark <whitequark@whitequark.org>
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# This file is Copyright (c) 2014 Yann Sionneau <ys@m-labs.hk>
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# This file is Copyright (c) 2018 bunnie <bunnie@kosagi.com>
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# This file is Copyright (c) 2019 Gabriel L. Somlo <gsomlo@gmail.com>
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# License: BSD
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from migen import log2_int
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cmds = {
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"PRECHARGE_ALL": "DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
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"MODE_REGISTER": "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
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"AUTO_REFRESH": "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS",
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"UNRESET": "DFII_CONTROL_ODT|DFII_CONTROL_RESET_N",
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"CKE": "DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N"
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}
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# SDR ----------------------------------------------------------------------------------------------
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def get_sdr_phy_init_sequence(phy_settings, timing_settings):
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cl = phy_settings.cl
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bl = 1
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mr = log2_int(bl) + (cl << 4)
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reset_dll = 1 << 8
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 20000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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return init_sequence, None
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# DDR ----------------------------------------------------------------------------------------------
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def get_ddr_phy_init_sequence(phy_settings, timing_settings):
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cl = phy_settings.cl
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bl = 4
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mr = log2_int(bl) + (cl << 4)
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emr = 0
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reset_dll = 1 << 8
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 20000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
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("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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return init_sequence, None
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# LPDDR --------------------------------------------------------------------------------------------
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def get_lpddr_phy_init_sequence(phy_settings, timing_settings):
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cl = phy_settings.cl
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bl = 4
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mr = log2_int(bl) + (cl << 4)
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emr = 0
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reset_dll = 1 << 8
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 20000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Extended Mode Register", emr, 2, cmds["MODE_REGISTER"], 0),
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("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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return init_sequence, None
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# DDR2 ---------------------------------------------------------------------------------------------
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def get_ddr2_phy_init_sequence(phy_settings, timing_settings):
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cl = phy_settings.cl
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bl = 4
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wr = 2
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mr = log2_int(bl) + (cl << 4) + (wr << 9)
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emr = 0
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emr2 = 0
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emr3 = 0
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reset_dll = 1 << 8
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ocd = 7 << 7
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 20000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Extended Mode Register 3", emr3, 3, cmds["MODE_REGISTER"], 0),
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("Load Extended Mode Register 2", emr2, 2, cmds["MODE_REGISTER"], 0),
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("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
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("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200),
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("Load Extended Mode Register / OCD Default", emr+ocd, 1, cmds["MODE_REGISTER"], 0),
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("Load Extended Mode Register / OCD Exit", emr, 1, cmds["MODE_REGISTER"], 0),
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]
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return init_sequence, None
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# DDR3 ---------------------------------------------------------------------------------------------
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def get_ddr3_phy_init_sequence(phy_settings, timing_settings):
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cl = phy_settings.cl
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bl = 8
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cwl = phy_settings.cwl
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def format_mr0(bl, cl, wr, dll_reset):
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bl_to_mr0 = {
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4: 0b10,
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8: 0b00
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}
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cl_to_mr0 = {
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5: 0b0010,
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6: 0b0100,
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7: 0b0110,
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8: 0b1000,
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9: 0b1010,
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10: 0b1100,
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11: 0b1110,
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12: 0b0001,
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13: 0b0011,
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14: 0b0101
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}
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wr_to_mr0 = {
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16: 0b000,
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5: 0b001,
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6: 0b010,
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7: 0b011,
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8: 0b100,
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10: 0b101,
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12: 0b110,
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14: 0b111
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}
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mr0 = bl_to_mr0[bl]
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mr0 |= (cl_to_mr0[cl] & 1) << 2
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mr0 |= ((cl_to_mr0[cl] >> 1) & 0b111) << 4
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mr0 |= dll_reset << 8
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mr0 |= wr_to_mr0[wr] << 9
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return mr0
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def format_mr1(ron, rtt_nom):
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mr1 = ((ron >> 0) & 1) << 1
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mr1 |= ((ron >> 1) & 1) << 5
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mr1 |= ((rtt_nom >> 0) & 1) << 2
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mr1 |= ((rtt_nom >> 1) & 1) << 6
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mr1 |= ((rtt_nom >> 2) & 1) << 9
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return mr1
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def format_mr2(cwl, rtt_wr):
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mr2 = (cwl-5) << 3
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mr2 |= rtt_wr << 9
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return mr2
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z_to_rtt_nom = {
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"disabled" : 0,
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"60ohm" : 1,
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"120ohm" : 2,
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"40ohm" : 3,
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"20ohm" : 4,
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"30ohm" : 5
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}
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z_to_rtt_wr = {
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"disabled" : 0,
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"60ohm" : 1,
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"120ohm" : 2,
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}
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z_to_ron = {
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"40ohm" : 0,
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"34ohm" : 1,
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}
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# default electrical settings (point to point)
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rtt_nom = "60ohm"
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rtt_wr = "60ohm"
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ron = "34ohm"
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# override electrical settings if specified
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if hasattr(phy_settings, "rtt_nom"):
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rtt_nom = phy_settings.rtt_nom
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if hasattr(phy_settings, "rtt_wr"):
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rtt_wr = phy_settings.rtt_wr
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if hasattr(phy_settings, "ron"):
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ron = phy_settings.ron
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wr = max(timing_settings.tWTR*phy_settings.nphases, 5) # >= ceiling(tWR/tCK)
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mr0 = format_mr0(bl, cl, wr, 1)
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mr1 = format_mr1(z_to_ron[ron], z_to_rtt_nom[rtt_nom])
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mr2 = format_mr2(cwl, z_to_rtt_wr[rtt_wr])
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mr3 = 0
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init_sequence = [
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("Release reset", 0x0000, 0, cmds["UNRESET"], 50000),
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 10000),
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("Load Mode Register 2, CWL={0:d}".format(cwl), mr2, 2, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 3", mr3, 3, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 1", mr1, 1, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 0, CL={0:d}, BL={1:d}".format(cl, bl), mr0, 0, cmds["MODE_REGISTER"], 200),
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("ZQ Calibration", 0x0400, 0, "DFII_COMMAND_WE|DFII_COMMAND_CS", 200),
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]
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return init_sequence, mr1
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# DDR4 ---------------------------------------------------------------------------------------------
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def get_ddr4_phy_init_sequence(phy_settings, timing_settings):
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cl = phy_settings.cl
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bl = 8
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cwl = phy_settings.cwl
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def format_mr0(bl, cl, wr, dll_reset):
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bl_to_mr0 = {
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4: 0b10,
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8: 0b00
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}
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cl_to_mr0 = {
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9: 0b00000,
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10: 0b00001,
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11: 0b00010,
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12: 0b00011,
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13: 0b00100,
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14: 0b00101,
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15: 0b00110,
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16: 0b00111,
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18: 0b01000,
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20: 0b01001,
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22: 0b01010,
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24: 0b01011,
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23: 0b01100,
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17: 0b01101,
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19: 0b01110,
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21: 0b01111,
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25: 0b10000,
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26: 0b10001,
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27: 0b10010,
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28: 0b10011,
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29: 0b10100,
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30: 0b10101,
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31: 0b10110,
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32: 0b10111,
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}
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wr_to_mr0 = {
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10: 0b0000,
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12: 0b0001,
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14: 0b0010,
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16: 0b0011,
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18: 0b0100,
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20: 0b0101,
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24: 0b0110,
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22: 0b0111,
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26: 0b1000,
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28: 0b1001,
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}
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mr0 = bl_to_mr0[bl]
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mr0 |= (cl_to_mr0[cl] & 0b1) << 2
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mr0 |= ((cl_to_mr0[cl] >> 1) & 0b111) << 4
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mr0 |= ((cl_to_mr0[cl] >> 4) & 0b1) << 12
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mr0 |= dll_reset << 8
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mr0 |= (wr_to_mr0[wr] & 0b111) << 9
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mr0 |= (wr_to_mr0[wr] >> 3) << 13
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return mr0
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def format_mr1(dll_enable, ron, rtt_nom):
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mr1 = dll_enable
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mr1 |= ((ron >> 0) & 0b1) << 1
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mr1 |= ((ron >> 1) & 0b1) << 2
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mr1 |= ((rtt_nom >> 0) & 0b1) << 8
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mr1 |= ((rtt_nom >> 1) & 0b1) << 9
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mr1 |= ((rtt_nom >> 2) & 0b1) << 10
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return mr1
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def format_mr2(cwl, rtt_wr):
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cwl_to_mr2 = {
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9: 0b000,
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10: 0b001,
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11: 0b010,
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12: 0b011,
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14: 0b100,
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16: 0b101,
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18: 0b110,
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20: 0b111
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}
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mr2 = cwl_to_mr2[cwl] << 3
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mr2 |= rtt_wr << 9
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return mr2
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def format_mr3(fine_refresh_mode):
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fine_refresh_mode_to_mr3 = {
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"1x": 0b000,
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"2x": 0b001,
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"4x": 0b010
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}
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mr3 = fine_refresh_mode_to_mr3[fine_refresh_mode] << 6
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return mr3
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def format_mr6(tccd):
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tccd_to_mr6 = {
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4: 0b000,
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5: 0b001,
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6: 0b010,
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7: 0b011,
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8: 0b100
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}
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mr6 = tccd_to_mr6[tccd] << 10
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return mr6
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z_to_rtt_nom = {
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"disabled" : 0b000,
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"60ohm" : 0b001,
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"120ohm" : 0b010,
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"40ohm" : 0b011,
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"240ohm" : 0b100,
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"48ohm" : 0b101,
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"80ohm" : 0b110,
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"34ohm" : 0b111
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}
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z_to_rtt_wr = {
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"disabled" : 0b000,
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"120ohm" : 0b001,
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"240ohm" : 0b010,
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"high-z" : 0b011,
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"80ohm" : 0b100,
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}
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z_to_ron = {
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"34ohm" : 0b00,
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"48ohm" : 0b01,
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}
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# default electrical settings (point to point)
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rtt_nom = "40ohm"
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rtt_wr = "120ohm"
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ron = "34ohm"
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# override electrical settings if specified
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if hasattr(phy_settings, "rtt_nom"):
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rtt_nom = phy_settings.rtt_nom
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if hasattr(phy_settings, "rtt_wr"):
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rtt_wr = phy_settings.rtt_wr
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if hasattr(phy_settings, "ron"):
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ron = phy_settings.ron
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wr = max(timing_settings.tWTR*phy_settings.nphases, 10) # >= ceiling(tWR/tCK)
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mr0 = format_mr0(bl, cl, wr, 1)
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mr1 = format_mr1(1, z_to_ron[ron], z_to_rtt_nom[rtt_nom])
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mr2 = format_mr2(cwl, z_to_rtt_wr[rtt_wr])
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mr3 = format_mr3(timing_settings.fine_refresh_mode)
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mr4 = 0
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mr5 = 0
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mr6 = format_mr6(4) # FIXME: tCCD
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init_sequence = [
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("Release reset", 0x0000, 0, cmds["UNRESET"], 50000),
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 10000),
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("Load Mode Register 3", mr3, 3, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 6", mr6, 6, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 5", mr5, 5, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 4", mr4, 4, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 2, CWL={0:d}".format(cwl), mr2, 2, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 1", mr1, 1, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 0, CL={0:d}, BL={1:d}".format(cl, bl), mr0, 0, cmds["MODE_REGISTER"], 200),
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("ZQ Calibration", 0x0400, 0, "DFII_COMMAND_WE|DFII_COMMAND_CS", 200),
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]
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return init_sequence, mr1
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# Init Sequence ------------------------------------------------------------------------------------
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def get_sdram_phy_init_sequence(phy_settings, timing_settings):
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return {
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"SDR" : get_sdr_phy_init_sequence,
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"DDR" : get_ddr_phy_init_sequence,
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"LPDDR": get_lpddr_phy_init_sequence,
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"DDR2" : get_ddr2_phy_init_sequence,
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"DDR3" : get_ddr3_phy_init_sequence,
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"DDR4" : get_ddr4_phy_init_sequence,
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}[phy_settings.memtype](phy_settings, timing_settings)
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# C Header -----------------------------------------------------------------------------------------
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def get_sdram_phy_c_header(phy_settings, timing_settings):
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r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n"
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r += "#include <hw/common.h>\n#include <generated/csr.h>\n#include <hw/flags.h>\n\n"
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nphases = phy_settings.nphases
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r += "#define DFII_NPHASES "+str(nphases)+"\n\n"
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r += "static void cdelay(int i);\n"
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# commands_px functions
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for n in range(nphases):
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r += """
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__attribute__((unused)) static void command_p{n}(int cmd)
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{{
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sdram_dfii_pi{n}_command_write(cmd);
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sdram_dfii_pi{n}_command_issue_write(1);
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}}""".format(n=str(n))
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r += "\n\n"
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# rd/wr access macros
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r += """
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#define sdram_dfii_pird_address_write(X) sdram_dfii_pi{rdphase}_address_write(X)
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#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi{wrphase}_address_write(X)
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#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi{rdphase}_baddress_write(X)
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#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi{wrphase}_baddress_write(X)
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#define command_prd(X) command_p{rdphase}(X)
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#define command_pwr(X) command_p{wrphase}(X)
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""".format(rdphase=str(phy_settings.rdphase), wrphase=str(phy_settings.wrphase))
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r += "\n"
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#
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# sdrrd/sdrwr functions utilities
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#
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r += "#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE\n"
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sdram_dfii_pix_wrdata_addr = []
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for n in range(nphases):
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sdram_dfii_pix_wrdata_addr.append("CSR_SDRAM_DFII_PI{n}_WRDATA_ADDR".format(n=n))
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r += """
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const unsigned long sdram_dfii_pix_wrdata_addr[DFII_NPHASES] = {{
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|
\t{sdram_dfii_pix_wrdata_addr}
|
|
}};
|
|
""".format(sdram_dfii_pix_wrdata_addr=",\n\t".join(sdram_dfii_pix_wrdata_addr))
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|
|
|
sdram_dfii_pix_rddata_addr = []
|
|
for n in range(nphases):
|
|
sdram_dfii_pix_rddata_addr.append("CSR_SDRAM_DFII_PI{n}_RDDATA_ADDR".format(n=n))
|
|
r += """
|
|
const unsigned long sdram_dfii_pix_rddata_addr[DFII_NPHASES] = {{
|
|
\t{sdram_dfii_pix_rddata_addr}
|
|
}};
|
|
""".format(sdram_dfii_pix_rddata_addr=",\n\t".join(sdram_dfii_pix_rddata_addr))
|
|
r += "\n"
|
|
|
|
init_sequence, mr1 = get_sdram_phy_init_sequence(phy_settings, timing_settings)
|
|
|
|
if phy_settings.memtype in ["DDR3", "DDR4"]:
|
|
# the value of MR1 needs to be modified during write leveling
|
|
r += "#define DDRX_MR1 {}\n\n".format(mr1)
|
|
|
|
r += "static void init_sequence(void)\n{\n"
|
|
for comment, a, ba, cmd, delay in init_sequence:
|
|
r += "\t/* {0} */\n".format(comment)
|
|
r += "\tsdram_dfii_pi0_address_write({0:#x});\n".format(a)
|
|
r += "\tsdram_dfii_pi0_baddress_write({0:d});\n".format(ba)
|
|
if cmd[:12] == "DFII_CONTROL":
|
|
r += "\tsdram_dfii_control_write({0});\n".format(cmd)
|
|
else:
|
|
r += "\tcommand_p0({0});\n".format(cmd)
|
|
if delay:
|
|
r += "\tcdelay({0:d});\n".format(delay)
|
|
r += "\n"
|
|
r += "}\n"
|
|
|
|
r += "#endif\n"
|
|
|
|
return r
|
|
|
|
# Python Header ------------------------------------------------------------------------------------
|
|
|
|
def get_sdram_phy_py_header(phy_settings, timing_settings):
|
|
r = ""
|
|
r += "dfii_control_sel = 0x01\n"
|
|
r += "dfii_control_cke = 0x02\n"
|
|
r += "dfii_control_odt = 0x04\n"
|
|
r += "dfii_control_reset_n = 0x08\n"
|
|
r += "\n"
|
|
r += "dfii_command_cs = 0x01\n"
|
|
r += "dfii_command_we = 0x02\n"
|
|
r += "dfii_command_cas = 0x04\n"
|
|
r += "dfii_command_ras = 0x08\n"
|
|
r += "dfii_command_wrdata = 0x10\n"
|
|
r += "dfii_command_rddata = 0x20\n"
|
|
r += "\n"
|
|
|
|
init_sequence, mr1 = get_sdram_phy_init_sequence(phy_settings, timing_settings)
|
|
|
|
if mr1 is not None:
|
|
r += "ddrx_mr1 = 0x{:x}\n".format(mr1)
|
|
r += "\n"
|
|
|
|
r += "init_sequence = [\n"
|
|
for comment, a, ba, cmd, delay in init_sequence:
|
|
r += " "
|
|
r += "(\"" + comment + "\", "
|
|
r += str(a) + ", "
|
|
r += str(ba) + ", "
|
|
r += cmd.lower() + ", "
|
|
r += str(delay) + "),"
|
|
r += "\n"
|
|
r += "]\n"
|
|
return r
|