Small footprint and configurable DRAM core
Go to file
Florent Kermarrec 812d7dd7f0 frontend/bist: reword bist, add simulation, seems to work but need more testing 2016-05-03 19:24:33 +02:00
example_designs update code, start bankmachine refactoring and remove old code (will be rewritten) 2015-09-15 10:22:39 +02:00
litedram frontend/bist: reword bist, add simulation, seems to work but need more testing 2016-05-03 19:24:33 +02:00
test frontend/bist: reword bist, add simulation, seems to work but need more testing 2016-05-03 19:24:33 +02:00
LICENSE init from LiteX/MiSoC 2016-04-29 07:44:30 +02:00
README init from LiteX/MiSoC 2016-04-29 07:44:30 +02:00
setup.py init from LiteX/MiSoC 2016-04-29 07:44:30 +02:00

README

         __   _ __      ___  ___  ___   __  ___
        / /  (_) /____ / _ \/ _ \/ _ | /  |/  /
       / /__/ / __/ -_) // / , _/ __ |/ /|_/ /
      /____/_/\__/\__/____/_/|_/_/ |_/_/  /_/

           Copyright 2015-2016 / EnjoyDigital

       A small footprint and configurable DRAM core

                 ********************
                 * WORK IN PROGRESS *
                 ********************

[> Intro
---------
LiteDRAM provides a small footprint and configurable DRAM core.

LiteDRAM is part of LiteX libraries whose aims are to lower entry level of
complex FPGA cores by providing simple, elegant and efficient implementations
ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...

The core uses simple and specific streaming buses and will provides in the future
adapters to use standardized AXI or Avalon-ST streaming buses.

Since Python is used to describe the HDL, the core is highly and easily
configurable.

LiteDRAM uses technologies developed in partnership with M-Labs Ltd:
 - Migen enables generating HDL with Python in an efficient way.
 - MiSoC provides the basic blocks to build a powerful and small footprint SoC.

LiteDRAM can be used as a Migen/MiSoC library (by simply installing it
with the provided setup.py) or can be integrated with your standard design flow
by generating the verilog rtl that you will use as a standard core.

[> Features
-----------
XXX

[> Possible improvements
-------------------------
-
- ... See below Support and consulting :)

If you want to support these features, please contact us at florent [AT]
enjoy-digital.fr. You can also contact our partner on the public mailing list
devel [AT] lists.m-labs.hk.


[> Getting started
------------------
XXX

[> Simulations:
XXX

[> Tests :
XXX

[> License
-----------
LiteDRAM is released under the very permissive two-clause BSD license. Under
the terms of this license, you are authorized to use LiteDRAM for closed-source
proprietary designs.
Even though we do not require you to do so, those things are awesome, so please
do them if possible:
 - tell us that you are using LiteDRAM
 - cite LiteDRAM in publications related to research it has helped
 - send us feedback and suggestions for improvements
 - send us bug reports when something goes wrong
 - send us the modifications and improvements you have done to LiteDRAM.

[> Support and consulting
--------------------------
We love open-source hardware and like sharing our designs with others.

LiteDRAM is developed and maintained by EnjoyDigital. Initial development
is based on MiSoC's LASMICON.

If you would like to know more about LiteDRAM or if you are already a happy
user and would like to extend it for your needs, EnjoyDigital can provide standard
commercial support as well as consulting services.

So feel free to contact us, we'd love to work with you! (and eventually shorten
the list of the possible improvements :)

[> Contact
E-mail: florent [AT] enjoy-digital.fr