Greg Davill 0c8c707f24 ecp5ddrphy: Fix DELAYF initial value ... I've seen intermittent failures with recent builds. I suspect it is related to the DELAYF primitive not being correctly loaded with an initial value. Holding LOADN LOW ensures a value is correctly loaded.		2020-10-20 16:44:32 +10:30
..
core	phy/core: move rd/wrcmdphase and computation to Multiplexer.	2020-10-01 11:26:04 +02:00
frontend	frontend/bist: expose core for observation.	2020-10-19 09:47:33 +02:00
phy	ecp5ddrphy: Fix DELAYF initial value	2020-10-20 16:44:32 +10:30
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	common/BitSlip: reset value to value.reset.	2020-10-08 19:40:40 +02:00
dfii.py	add SPDX License identifier to header and specify file is part of LiteDRAM.	2020-08-23 15:52:08 +02:00
gen.py	litedram/gen: update LiteDRAMECP5DDRPHYCRG (AsyncResetSynchronizer integrated in PLL).	2020-09-01 13:58:16 +02:00
init.py	init: Cast DDR4 RCD fine_speed to int	2020-10-13 13:10:31 +01:00
modules.py	modules: remove unnecessary memtypes.	2020-09-01 13:43:09 +02:00