Florent Kermarrec 8ec0bc678e modules: improve the way we define DDR4 banks/groups		2018-12-06 21:16:37 +01:00
..
core	core: make address_mapping a controller setting	2018-11-13 09:18:46 +01:00
frontend	frontend/axi: simplify LiteDRAMAXI2NativeW logic	2018-12-05 11:44:23 +01:00
phy	phy: add KUSDDRPHY to __init__.py	2018-12-06 21:15:47 +01:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	common: add DDR4 burst_length	2018-11-05 10:46:34 +01:00
dfii.py	multirank: one cs_n/cke/odt/clk per rank	2018-09-09 14:32:15 +02:00
modules.py	modules: improve the way we define DDR4 banks/groups	2018-12-06 21:16:37 +01:00
sdram_init.py	sdram_init: fix compilation	2018-11-05 10:46:47 +01:00