Piotr Binkowski 8fa7a93e5c phy/model: add support for sdram init for other memory types/widths ... Up until now init worked correctly only on 32-bit SDR modules, with this it should work at least with 64-bit wide DDR3, 128-bit DDR2 and 512-bit SDRAM		2020-01-31 11:14:32 +01:00
..
core	core/controller: cleanup ControllerSettings	2019-12-03 12:16:50 +01:00
frontend	frotend/wishbone: avoid NextValue(count, 0) duplication	2020-01-13 13:19:25 +01:00
phy	phy/model: add support for sdram init for other memory types/widths	2020-01-31 11:14:32 +01:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	global: improve presentation/readability	2019-11-30 10:53:11 +01:00
dfii.py	global: improve presentation/readability	2019-11-30 10:53:11 +01:00
gen.py	litedram_gen: cleanup/rename CRGs, update copyrights	2020-01-27 18:29:52 +01:00
init.py	modules/init: add DDR4 fine refresh mode support: x1, x2 and x4 (x1=previous and default behavior)	2019-12-03 12:20:32 +01:00
modules.py	modules: add M12L16161A	2020-01-22 16:31:13 +01:00