268 lines
12 KiB
Python
Executable File
268 lines
12 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import csv
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import logging
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import argparse
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from operator import and_
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from functools import reduce
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from itertools import zip_longest
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from migen import *
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from migen.genlib.misc import WaitTimer
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from litex.build.sim.config import SimConfig
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.tools.litex_sim import SimSoC
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from litedram.frontend.bist import _LiteDRAMBISTGenerator, _LiteDRAMBISTChecker
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from litedram.frontend.bist import _LiteDRAMPatternGenerator, _LiteDRAMPatternChecker
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# LiteDRAM Benchmark SoC ---------------------------------------------------------------------------
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class LiteDRAMBenchmarkSoC(SimSoC):
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def __init__(self,
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mode = "bist",
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sdram_module = "MT48LC16M16",
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sdram_data_width = 32,
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bist_base = 0x0000000,
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bist_end = 0x0100000,
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bist_length = 1024,
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bist_random = False,
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bist_alternating = False,
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num_generators = 1,
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num_checkers = 1,
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access_pattern = None,
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**kwargs):
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assert mode in ["bist", "pattern"]
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assert not (mode == "pattern" and access_pattern is None)
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# SimSoC -----------------------------------------------------------------------------------
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SimSoC.__init__(self,
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with_sdram = True,
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sdram_module = sdram_module,
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sdram_data_width = sdram_data_width,
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**kwargs
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)
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# BIST/Pattern Generator / Checker ---------------------------------------------------------
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if mode == "pattern":
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make_generator = lambda: _LiteDRAMPatternGenerator(self.sdram.crossbar.get_port(), init=access_pattern)
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make_checker = lambda: _LiteDRAMPatternChecker(self.sdram.crossbar.get_port(), init=access_pattern)
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if mode == "bist":
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make_generator = lambda: _LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
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make_checker = lambda: _LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
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generators = [make_generator() for _ in range(num_generators)]
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checkers = [make_checker() for _ in range(num_checkers)]
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self.submodules += generators + checkers
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if mode == "pattern":
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def bist_config(module):
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return []
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if not bist_alternating:
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address_set = set()
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for addr, _ in access_pattern:
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assert addr not in address_set, \
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"Duplicate address 0x%08x in access_pattern, write will overwrite previous value!" % addr
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address_set.add(addr)
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if mode == "bist":
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# Make sure that we perform at least one access
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bist_length = max(bist_length, self.sdram.controller.interface.data_width // 8)
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def bist_config(module):
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return [
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module.base.eq(bist_base),
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module.end.eq(bist_end),
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module.length.eq(bist_length),
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module.random_addr.eq(bist_random),
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]
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assert not (bist_random and not bist_alternating), \
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"Write to random address may overwrite previously written data before reading!"
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# Check address correctness
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assert bist_end > bist_base
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assert bist_end <= 2**(len(generators[0].end)) - 1, "End address outside of range"
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bist_addr_range = bist_end - bist_base
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assert bist_addr_range > 0 and bist_addr_range & (bist_addr_range - 1) == 0, \
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"Length of the address range must be a power of 2"
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def combined_read(modules, signal, operator):
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sig = Signal()
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self.comb += sig.eq(reduce(operator, (getattr(m, signal) for m in modules)))
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return sig
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def combined_write(modules, signal):
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sig = Signal()
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self.comb += [getattr(m, signal).eq(sig) for m in modules]
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return sig
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# Sequencer --------------------------------------------------------------------------------
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class LiteDRAMCoreControl(Module, AutoCSR):
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def __init__(self):
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self.init_done = CSRStorage()
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self.init_error = CSRStorage()
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self.submodules.ddrctrl = ddrctrl = LiteDRAMCoreControl()
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self.add_csr("ddrctrl")
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display = Signal()
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finish = Signal()
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self.submodules.fsm = fsm = FSM(reset_state="WAIT-INIT")
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fsm.act("WAIT-INIT",
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If(self.ddrctrl.init_done.storage, # Written by CPU when initialization is done
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NextState("BIST-GENERATOR")
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)
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)
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if bist_alternating:
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# Force generators to wait for checkers and vice versa. Connect them in pairs, with each
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# unpaired connected to the first of the others.
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bist_connections = []
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for generator, checker in zip_longest(generators, checkers):
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g = generator or generators[0]
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c = checker or checkers[0]
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bist_connections += [
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g.run_cascade_in.eq(c.run_cascade_out),
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c.run_cascade_in.eq(g.run_cascade_out),
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]
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fsm.act("BIST-GENERATOR",
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combined_write(generators + checkers, "start").eq(1),
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*bist_connections,
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*map(bist_config, generators + checkers),
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If(combined_read(checkers, "done", and_),
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NextState("DISPLAY")
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)
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)
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else:
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fsm.act("BIST-GENERATOR",
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combined_write(generators, "start").eq(1),
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*map(bist_config, generators),
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If(combined_read(generators, "done", and_),
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NextState("BIST-CHECKER")
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)
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)
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fsm.act("BIST-CHECKER",
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combined_write(checkers, "start").eq(1),
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*map(bist_config, checkers),
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If(combined_read(checkers, "done", and_),
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NextState("DISPLAY")
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)
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)
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fsm.act("DISPLAY",
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display.eq(1),
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NextState("FINISH")
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)
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fsm.act("FINISH",
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finish.eq(1)
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)
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# Simulation Results -----------------------------------------------------------------------
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def max_signal(signals):
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signals = iter(signals)
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s = next(signals)
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out = Signal(len(s))
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self.comb += out.eq(s)
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for curr in signals:
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prev = out
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out = Signal(max(len(prev), len(curr)))
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self.comb += If(prev > curr, out.eq(prev)).Else(out.eq(curr))
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return out
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generator_ticks = max_signal((g.ticks for g in generators))
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checker_errors = max_signal((c.errors for c in checkers))
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checker_ticks = max_signal((c.ticks for c in checkers))
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self.sync += [
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If(display,
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Display("BIST-GENERATOR ticks: %08d", generator_ticks),
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Display("BIST-CHECKER errors: %08d", checker_errors),
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Display("BIST-CHECKER ticks: %08d", checker_ticks),
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)
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]
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# Simulation End ---------------------------------------------------------------------------
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end_timer = WaitTimer(2**16)
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self.submodules += end_timer
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self.comb += end_timer.wait.eq(finish)
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self.sync += If(end_timer.done, Finish())
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# Build --------------------------------------------------------------------------------------------
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def load_access_pattern(filename):
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with open(filename, newline="") as f:
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reader = csv.reader(f)
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access_pattern = [(int(addr, 0), int(data, 0)) for addr, data in reader]
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return access_pattern
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def main():
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parser = argparse.ArgumentParser(description="LiteDRAM Benchmark SoC Simulation")
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builder_args(parser)
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soc_sdram_args(parser)
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parser.add_argument("--threads", default=1, help="Set number of threads (default=1)")
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parser.add_argument("--sdram-module", default="MT48LC16M16", help="Select SDRAM chip")
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parser.add_argument("--sdram-data-width", default=32, help="Set SDRAM chip data width")
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parser.add_argument("--sdram-verbosity", default=0, help="Set SDRAM checker verbosity")
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parser.add_argument("--trace", action="store_true", help="Enable VCD tracing")
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parser.add_argument("--trace-start", default=0, help="Cycle to start VCD tracing")
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parser.add_argument("--trace-end", default=-1, help="Cycle to end VCD tracing")
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parser.add_argument("--opt-level", default="O0", help="Compilation optimization level")
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parser.add_argument("--bist-base", default="0x00000000", help="Base address of the test (default=0)")
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parser.add_argument("--bist-length", default="1024", help="Length of the test (default=1024)")
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parser.add_argument("--bist-random", action="store_true", help="Use random data during the test")
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parser.add_argument("--bist-alternating", action="store_true", help="Perform alternating writes/reads (WRWRWR... instead of WWW...RRR...)")
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parser.add_argument("--num-generators", default=1, help="Number of BIST generators")
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parser.add_argument("--num-checkers", default=1, help="Number of BIST checkers")
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parser.add_argument("--access-pattern", help="Load access pattern (address, data) from CSV (ignores --bist-*)")
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parser.add_argument("--log-level", default="info", help="Set logging verbosity",
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choices=["critical", "error", "warning", "info", "debug"])
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args = parser.parse_args()
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root_logger = logging.getLogger()
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root_logger.setLevel(getattr(logging, args.log_level.upper()))
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soc_kwargs = soc_sdram_argdict(args)
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builder_kwargs = builder_argdict(args)
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sim_config = SimConfig(default_clk="sys_clk")
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sim_config.add_module("serial2console", "serial")
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# Configuration --------------------------------------------------------------------------------
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soc_kwargs["uart_name"] = "sim"
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soc_kwargs["sdram_module"] = args.sdram_module
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soc_kwargs["sdram_data_width"] = int(args.sdram_data_width)
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soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity)
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soc_kwargs["bist_base"] = int(args.bist_base, 0)
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soc_kwargs["bist_length"] = int(args.bist_length, 0)
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soc_kwargs["bist_random"] = args.bist_random
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soc_kwargs["bist_alternating"] = args.bist_alternating
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soc_kwargs["num_generators"] = int(args.num_generators)
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soc_kwargs["num_checkers"] = int(args.num_checkers)
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if args.access_pattern:
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soc_kwargs["access_pattern"] = load_access_pattern(args.access_pattern)
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# SoC ------------------------------------------------------------------------------------------
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soc = LiteDRAMBenchmarkSoC(mode="pattern" if args.access_pattern else "bist", **soc_kwargs)
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# Build/Run ------------------------------------------------------------------------------------
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builder_kwargs["csr_csv"] = "csr.csv"
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builder = Builder(soc, **builder_kwargs)
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vns = builder.build(
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threads = args.threads,
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sim_config = sim_config,
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opt_level = args.opt_level,
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trace = args.trace,
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trace_start = int(args.trace_start),
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trace_end = int(args.trace_end)
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)
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if __name__ == "__main__":
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main()
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