220 lines
9.7 KiB
Python
220 lines
9.7 KiB
Python
# This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
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# License: BSD
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import os
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import csv
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import unittest
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import litedram.modules
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from litedram.modules import SDRAMModule, DDR3SPDData
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def load_spd_reference(filename):
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"""Load reference SPD data from a CSV file
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Micron reference SPD data can be obtained from:
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https://www.micron.com/support/tools-and-utilities/serial-presence-detect
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"""
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script_dir = os.path.dirname(os.path.realpath(__file__))
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path = os.path.join(script_dir, "spd_data", filename)
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data = [0] * 512
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with open(path) as f:
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reader = csv.DictReader(f)
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for row in reader:
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address = row["Byte Number"]
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value = row["Byte Value"]
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# Ignore ranges (data we care about is specified per byte anyway)
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if len(address.split("-")) == 1:
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data[int(address)] = int(value, 16)
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return data
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class TestSPD(unittest.TestCase):
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def test_tck_to_speedgrade(self):
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# Verify that speedgrade transfer rates are calculated correctly from tck
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tck_to_speedgrade = {
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2.5: 800,
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1.875: 1066,
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1.5: 1333,
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1.25: 1600,
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1.071: 1866,
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0.938: 2133,
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}
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for tck, speedgrade in tck_to_speedgrade.items():
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self.assertEqual(speedgrade, DDR3SPDData.speedgrade_freq(tck))
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def test_spd_data(self):
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# Verify that correct _spd_data is added to SDRAMModule
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data = load_spd_reference("MT16KTF1G64HZ-1G6P1.csv")
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module = SDRAMModule.from_spd_data(data, 125e6)
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self.assertEqual(module._spd_data, data)
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def compare_geometry(self, module, module_ref):
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self.assertEqual(module.nbanks, module_ref.nbanks)
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self.assertEqual(module.nrows, module_ref.nrows)
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self.assertEqual(module.ncols, module_ref.ncols)
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def compare_technology_timings(self, module, module_ref, omit=None):
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timings = {"tREFI", "tWTR", "tCCD", "tRRD", "tZQCS"}
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if omit is not None:
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timings -= omit
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for timing in timings:
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txx = getattr(module.technology_timings, timing)
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txx_ref = getattr(module_ref.technology_timings, timing)
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with self.subTest(txx=timing):
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self.assertEqual(txx, txx_ref)
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def compare_speedgrade_timings(self, module, module_ref, omit=None):
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timings = {"tRP", "tRCD", "tWR", "tRFC", "tFAW", "tRAS"}
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if omit is not None:
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timings -= omit
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for freq, speedgrade_timings in module.speedgrade_timings.items():
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if freq == "default":
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continue
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for timing in timings:
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txx = getattr(speedgrade_timings, timing)
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txx_ref = getattr(module_ref.speedgrade_timings[freq], timing)
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with self.subTest(freq=freq, txx=timing):
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self.assertEqual(txx, txx_ref)
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def compare_modules(self, module, module_ref, omit=None):
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self.assertEqual(module.memtype, module_ref.memtype)
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self.assertEqual(module.rate, module_ref.rate)
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self.compare_geometry(module, module_ref)
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self.compare_technology_timings(module, module_ref, omit=omit)
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self.compare_speedgrade_timings(module, module_ref, omit=omit)
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def test_MT16KTF1G64HZ(self):
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kwargs = dict(clk_freq=125e6, rate="1:4")
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module_ref = litedram.modules.MT16KTF1G64HZ(**kwargs)
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with self.subTest(speedgrade="-1G6"):
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data = load_spd_reference("MT16KTF1G64HZ-1G6P1.csv")
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module = SDRAMModule.from_spd_data(data, kwargs["clk_freq"])
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self.compare_modules(module, module_ref)
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sgt = module.speedgrade_timings["1600"]
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self.assertEqual(sgt.tRP, 13.125)
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self.assertEqual(sgt.tRCD, 13.125)
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self.assertEqual(sgt.tRP + sgt.tRAS, 48.125)
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with self.subTest(speedgrade="-1G9"):
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data = load_spd_reference("MT16KTF1G64HZ-1G9E1.csv")
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module = SDRAMModule.from_spd_data(data, kwargs["clk_freq"])
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# tRRD it different for this speedgrade
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self.compare_modules(module, module_ref, omit={"tRRD"})
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self.assertEqual(module.technology_timings.tRRD, (4, 5))
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sgt = module.speedgrade_timings["1866"]
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self.assertEqual(sgt.tRP, 13.125)
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self.assertEqual(sgt.tRCD, 13.125)
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self.assertEqual(sgt.tRP + sgt.tRAS, 47.125)
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def test_MT18KSF1G72HZ(self):
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kwargs = dict(clk_freq=125e6, rate="1:4")
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module_ref = litedram.modules.MT18KSF1G72HZ(**kwargs)
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with self.subTest(speedgrade="-1G6"):
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data = load_spd_reference("MT18KSF1G72HZ-1G6E2.csv")
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module = SDRAMModule.from_spd_data(data, kwargs["clk_freq"])
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self.compare_modules(module, module_ref)
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sgt = module.speedgrade_timings["1600"]
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self.assertEqual(sgt.tRP, 13.125)
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self.assertEqual(sgt.tRCD, 13.125)
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self.assertEqual(sgt.tRP + sgt.tRAS, 48.125)
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with self.subTest(speedgrade="-1G4"):
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data = load_spd_reference("MT18KSF1G72HZ-1G4E2.csv")
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module = SDRAMModule.from_spd_data(data, kwargs["clk_freq"])
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self.compare_modules(module, module_ref)
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sgt = module.speedgrade_timings["1333"]
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self.assertEqual(sgt.tRP, 13.125)
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self.assertEqual(sgt.tRCD, 13.125)
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self.assertEqual(sgt.tRP + sgt.tRAS, 49.125)
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def test_MT8JTF12864(self):
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kwargs = dict(clk_freq=125e6, rate="1:4")
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module_ref = litedram.modules.MT8JTF12864(**kwargs)
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data = load_spd_reference("MT8JTF12864AZ-1G4G1.csv")
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module = SDRAMModule.from_spd_data(data, kwargs["clk_freq"])
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self.compare_modules(module, module_ref)
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sgt = module.speedgrade_timings["1333"]
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self.assertEqual(sgt.tRP, 13.125)
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self.assertEqual(sgt.tRCD, 13.125)
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self.assertEqual(sgt.tRP + sgt.tRAS, 49.125)
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def test_MT8KTF51264(self):
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kwargs = dict(clk_freq=100e6, rate="1:4")
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module_ref = litedram.modules.MT8KTF51264(**kwargs)
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with self.subTest(speedgrade="-1G4"):
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data = load_spd_reference("MT8KTF51264HZ-1G4E1.csv")
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module = SDRAMModule.from_spd_data(data, kwargs["clk_freq"])
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self.compare_modules(module, module_ref)
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sgt = module.speedgrade_timings["1333"]
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self.assertEqual(sgt.tRP, 13.125)
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self.assertEqual(sgt.tRCD, 13.125)
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self.assertEqual(sgt.tRP + sgt.tRAS, 49.125)
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with self.subTest(speedgrade="-1G6"):
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data = load_spd_reference("MT8KTF51264HZ-1G6E1.csv")
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module = SDRAMModule.from_spd_data(data, kwargs["clk_freq"])
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self.compare_modules(module, module_ref)
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sgt = module.speedgrade_timings["1600"]
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self.assertEqual(sgt.tRP, 13.125)
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self.assertEqual(sgt.tRCD, 13.125)
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self.assertEqual(sgt.tRP + sgt.tRAS, 48.125)
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with self.subTest(speedgrade="-1G9"):
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data = load_spd_reference("MT8KTF51264HZ-1G9P1.csv")
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module = SDRAMModule.from_spd_data(data, kwargs["clk_freq"])
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# tRRD different for this timing
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self.compare_modules(module, module_ref, omit={"tRRD"})
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self.assertEqual(module.technology_timings.tRRD, (4, 5))
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sgt = module.speedgrade_timings["1866"]
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self.assertEqual(sgt.tRP, 13.125)
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self.assertEqual(sgt.tRCD, 13.125)
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self.assertEqual(sgt.tRP + sgt.tRAS, 47.125)
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def test_MTA4ATF51264HZ_parsing(self):
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kwargs = dict(clk_freq=100e6, rate="1:4")
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with self.subTest(speedgrade="-2G3"):
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data = load_spd_reference("MTA4ATF51264HZ-2G3B1.csv")
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module = SDRAMModule.from_spd_data(data, kwargs["clk_freq"])
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sgt = module.speedgrade_timings["2400"]
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self.assertEqual(sgt.tRP, 13.75)
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self.assertEqual(sgt.tRCD, 13.75)
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self.assertEqual(sgt.tRP + sgt.tRAS, 45.75)
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with self.subTest(speedgrade="-3G2"):
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data = load_spd_reference("MTA4ATF51264HZ-3G2E1.csv")
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module = SDRAMModule.from_spd_data(data, kwargs["clk_freq"])
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sgt = module.speedgrade_timings["3200"]
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self.assertEqual(sgt.tRP, 13.75)
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self.assertEqual(sgt.tRCD, 13.75)
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self.assertEqual(sgt.tRP + sgt.tRAS, 45.75)
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# FIXME: when setting timings as seen in SPD, DRAM leveling fails
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@unittest.skip("Using timings from SPD fails DRAM initialzation on this module")
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def test_MTA4ATF51264HZ(self):
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kwargs = dict(clk_freq=100e6, rate="1:4")
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module_ref = litedram.modules.MTA4ATF51264HZ(**kwargs)
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with self.subTest(speedgrade="-2G3"):
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data = load_spd_reference("MTA4ATF51264HZ-2G3B1.csv")
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module = SDRAMModule.from_spd_data(data, kwargs["clk_freq"])
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self.compare_modules(module, module_ref)
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sgt = module.speedgrade_timings["2400"]
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self.assertEqual(sgt.tRP, 13.75)
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self.assertEqual(sgt.tRCD, 13.75)
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self.assertEqual(sgt.tRP + sgt.tRAS, 45.75)
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with self.subTest(speedgrade="-3G2"):
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data = load_spd_reference("MTA4ATF51264HZ-3G2E1.csv")
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module = SDRAMModule.from_spd_data(data, kwargs["clk_freq"])
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self.compare_modules(module, module_ref)
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sgt = module.speedgrade_timings["3200"]
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self.assertEqual(sgt.tRP, 13.75)
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self.assertEqual(sgt.tRCD, 13.75)
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self.assertEqual(sgt.tRP + sgt.tRAS, 45.75)
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