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litedram/test
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Florent Kermarrec 2b20c11e2d add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility 
- LiteDRAMPort -> LiteDRAMNativePort
- aw -> address_width
- dw -> data_width
- cd -> clock_domain
 		2018-08-21 13:21:04 +02:00
..
__init__.py update code, start bankmachine refactoring and remove old code (will be rewritten) 2015-09-15 10:22:39 +02:00
common.py replace litex.gen imports with migen imports 2018-02-23 13:39:23 +01:00
test_bist.py test: update 2018-08-09 10:54:42 +02:00
test_bist_async.py add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility 2018-08-21 13:21:04 +02:00
test_downconverter.py add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility 2018-08-21 13:21:04 +02:00
test_upconverter.py add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility 2018-08-21 13:21:04 +02:00