litedram/litedram
2020-02-03 13:35:49 +01:00
..
core core/controller: cleanup ControllerSettings 2019-12-03 12:16:50 +01:00
frontend frontend/dma: add optional CSR control 2020-01-30 15:21:37 +01:00
phy phy/model: fix case when not converting init data width 2020-02-03 13:35:49 +01:00
__init__.py
common.py global: improve presentation/readability 2019-11-30 10:53:11 +01:00
dfii.py global: improve presentation/readability 2019-11-30 10:53:11 +01:00
gen.py litedram_gen: cleanup/rename CRGs, update copyrights 2020-01-27 18:29:52 +01:00
init.py modules/init: add DDR4 fine refresh mode support: x1, x2 and x4 (x1=previous and default behavior) 2019-12-03 12:20:32 +01:00
modules.py modules: add M12L16161A 2020-01-22 16:31:13 +01:00