191 lines
9.2 KiB
Plaintext
191 lines
9.2 KiB
Plaintext
Disclaimer of Warranty:
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-----------------------
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This software code and all associated documentation, comments or other
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information (collectively "Software") is provided "AS IS" without
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warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
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DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
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TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
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OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
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WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
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OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
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FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
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THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
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ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
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OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
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ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
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INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
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WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
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OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
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THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
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DAMAGES. Because some jurisdictions prohibit the exclusion or
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limitation of liability for consequential or incidental damages, the
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above limitation may not apply to you.
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Copyright 2003 Micron Technology, Inc. All rights reserved.
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Getting Started:
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----------------
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Unzip the included files to a folder.
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Compile ddr3.v and tb.v in a verilog simulator.
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Simulate the top level test bench tb.
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Or, if you are using the ModelSim simulator, type "do tb.do" at the prompt.
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File Descriptions:
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------------------
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ddr3.v -ddr3 model
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ddr3_mcp.v -structural wrapper for ddr3 - multi-chip package model
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ddr3_module.v -structural wrapper for ddr3 - module model
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1024Mb_ddr3_parameters.vh -file that contains all 1Gb parameters used by the model
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2048Mb_ddr3_parameters.vh -file that contains all 2Gb parameters used by the model
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4096Mb_ddr3_parameters.vh -file that contains all 4Gb parameters used by the model
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8192Mb_ddr3_parameters.vh -file that contains all 8Gb parameters used by the model
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readme.txt -this file
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tb.v -ddr3 model test bench
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subtest.vh -example test included by the test bench.
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Defining the Speed Grade:
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-------------------------
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The verilog compiler directive "`define" may be used to choose between
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multiple speed grades supported by the ddr3 model. Allowable speed
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grades are listed in the ddr3_parameters.vh file and begin with the
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letters "sg". The speed grade is used to select a set of timing
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parameters for the ddr3 model. The following are examples of defining
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the speed grade.
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simulator command line
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--------- ------------
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ModelSim vlog +define+sg25 ddr3.v
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VCS vcs +define+sg25 ddr3.v
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NC-Verilog ncverilog +define+sg25 ddr3.v
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Defining the Organization:
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--------------------------
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The verilog compiler directive "`define" may be used to choose between
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multiple organizations supported by the ddr3 model. Valid
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organizations include "x4", "x8", and x16, and are listed in the
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ddr3_parameters.vh file. The organization is used to select the amount
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of memory and the port sizes of the ddr3 model. The following are
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examples of defining the organization.
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simulator command line
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--------- ------------
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ModelSim vlog +define+x8 ddr3.v
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NC-Verilog ncverilog +define+x8 ddr3.v
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VCS vcs +define+x8 ddr3.v
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All combinations of speed grade and organization are considered valid
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by the ddr3 model even though a Micron part may not exist for every
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combination.
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Allocating Memory:
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------------------
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An associative array has been implemented to reduce the amount of
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static memory allocated by the ddr3 model. Each entry in the
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associative array is a burst length of eight in size. The number of
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entries in the associative array is controlled by the MEM_BITS
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parameter, and is equal to 2^MEM_BITS. For example, if the MEM_BITS
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parameter is equal to 10, the associative array will be large enough
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to store 1024 writes of burst length 8 to unique addresses. The
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following are examples of setting the MEM_BITS parameter to 8.
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simulator command line
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--------- ------------
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ModelSim vsim -GMEM_BITS=8 ddr3
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NC-Verilog ncverilog +defparam+ddr3.MEM_BITS=8 ddr3.v
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VCS vcs -pvalue+MEM_BITS=8 ddr3.v
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It is possible to allocate memory for every address supported by the
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ddr3 model by using the verilog compiler directive "`define MAX_MEM".
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This procedure will improve simulation performance at the expense of
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system memory. The following are examples of allocating memory for
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every address.
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Simulator command line
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--------- ------------
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ModelSim vlog +define+MAX_MEM ddr3.v
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NC-Verilog ncverilog +define+MAX_MEM ddr3.v
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VCS vcs +define+MAX_MEM ddr3.v
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**********************************************************************
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The following information is provided to assist the modeling engineer
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in creating multi-chip package (mcp) models. ddr3_mcp.v is a
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structural wrapper that instantiates ddr3 models. This wrapper can be
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used to create single, dual, or quad rank mcp models. From the
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perspective of the model, the only item that needs to be defined is the
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number of ranks.
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**********************************************************************
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Defining the Number of Ranks in a multi-chip package:
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----------------------------------------------------
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The verilog compiler directive "`define" may be used to choose between
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single, dual, and quad rank mcp configurations. The default is single
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rank if nothing is defined. Dual rank configuration can be selected by
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defining "DUAL_RANK" when the ddr3_mcp is compiled. Quad rank
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configuration can be selected by defining "QUAD_RANK" when the ddr3_mcp
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is compiled. The following are examples of defining a dual rank mcp
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configuration.
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simulator command line
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--------- ------------
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ModelSim vlog +define+DUAL_RANK ddr3.v ddr3_mcp.v
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NC-Verilog ncverilog +define+DUAL_RANK ddr3.v ddr3_mcp.v
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VCS vcs +define+DUAL_RANK ddr3.v ddr3_mcp.v
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**********************************************************************
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The following information is provided to assist the modeling engineer
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in creating DIMM models. ddr3_module.v is a structural wrapper that
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instantiates ddr3 models. This wrapper can be used to create UDIMM,
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RDIMM or SODIMM models. Other form factors are not supported
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(MiniDIMM, VLP DIMM, etc.). From the perspective of the model, the
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items that need to be defined are the number of ranks, the module
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type, and the presence of ECC. All combinations of ranks, module
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type, and ECC are considered valid by the ddr3_module model even
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though a Micron part may not exist for every combination.
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**********************************************************************
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Defining the Number of Ranks on a module:
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----------------------------------------
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The verilog compiler directive "`define" may be used to choose between
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single, dual, and quad rank module configurations. The default is single
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rank if nothing is defined. Dual rank configuration can be selected by
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defining "DUAL_RANK" when the ddr3_module is compiled. Quad rank
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configuration can be selected by defining "QUAD_RANK" when the ddr3_module
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is compiled. The following are examples of defining a dual rank module
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configuration.
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simulator command line
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--------- ------------
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ModelSim vlog +define+DUAL_RANK ddr3.v ddr3_module.v
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NC-Verilog ncverilog +define+DUAL_RANK ddr3.v ddr3_module.v
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VCS vcs +define+DUAL_RANK ddr3.v ddr3_module.v
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Defining the Module Type:
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-----------------------------------
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The verilog compiler directive "`define" may be used to choose between
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UDIMM, RDIMM, and SODIMM module configurations. The default is
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unregistered (UDIMM) if nothing is defined. SODIMM configuration can be
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selected by defining "SODIMM" when the ddr3_module is compiled. Registered
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configuration can be selected by defining "RDIMM" when the ddr3_module is
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compiled. The following are examples of defining a registered module
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configuration.
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simulator command line
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--------- ------------
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ModelSim vlog +define+RDIMM ddr3.v ddr3_module.v
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NC-Verilog ncverilog +define+RDIMM ddr3.v ddr3_module.v
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VCS vcs +define+RDIMM ddr3.v ddr3_module.v
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Defining the ECC for a module:
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-----------------------------
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The verilog compiler directive "`define" may be used to choose between
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ECC and nonECC module configurations. The default is nonECC if nothing
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is defined. ECC configuration can be selected by defining "ECC" when
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the ddr3_module is compiled. The following are examples of defining an
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ECC module configuration.
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simulator command line
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--------- ------------
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ModelSim vlog +define+ECC ddr3.v ddr3_module.v
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NC-Verilog ncverilog +define+ECC ddr3.v ddr3_module.v
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VCS vcs +define+ECC ddr3.v ddr3_module.v
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