Florent Kermarrec b93412bbdc examples: remove verilog simulation ... Simulation was here just to show how to do system level simulation adn required external component to work (stadalone init).		2019-05-10 13:05:48 +02:00
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arty_config.py	examples/litedram_gen: add DDR2 support	2019-02-21 23:32:23 +01:00
genesys2_config.py	examples/litedram_gen: add DDR2 support	2019-02-21 23:32:23 +01:00
litedram_gen.py	example/litedram_gen: reserve_nmi_interrupt no longer exists	2019-05-10 12:43:23 +02:00
nexys4ddr_config.py	examples: add nexys4ddr_config	2019-02-21 23:32:45 +01:00