Florent Kermarrec bf5883cd43 rename sdram_init to init		2019-09-09 11:42:02 +02:00
..
core	core/refresher: set cmd.valid to 0 when sequencer done	2019-08-30 08:55:38 +02:00
frontend	frontend/wishbone: split control/data paths (to avoid data muxes)	2019-09-03 12:44:07 +02:00
phy	phy/gensdrphy: add assertions on length of pads.dq/pads.dq	2019-08-04 15:06:34 +02:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	core: move timing controllers to common	2019-07-23 12:39:14 +02:00
dfii.py	add CONTRIBUTORS file and add copyright header to all files.	2019-06-23 23:59:10 +02:00
gen.py	litedram_gen: add wishbone user port support	2019-09-03 23:47:08 +02:00
init.py	rename sdram_init to init	2019-09-09 11:42:02 +02:00
modules.py	modules: add DDR3 MT8KTF51264 SO-DIMM	2019-09-09 08:47:29 +02:00