bfa1d6aa7e remove debug prints		2018-08-03 15:24:08 -04:00
..
core	Correct tWTR timing: 1) timing starts after the completion of the write burst, 2) We don't need to wait on switches if a write hasn't taken place recently	2018-07-31 13:31:49 -04:00
frontend	remove debug prints	2018-08-03 15:24:08 -04:00
phy	phy/s7ddrphy: add assert to make sure cmd/dat phases are not identical	2018-07-27 08:34:06 +02:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	Initial implementation of out of order controller	2018-08-03 15:21:17 -04:00
dfii.py	replace litex.gen imports with migen imports	2018-02-23 13:39:23 +01:00
modules.py	Add tRRD timing checks, and fix tFAW so it considers all banks	2018-07-30 23:45:52 -04:00