109 lines
3.9 KiB
Python
Executable File
109 lines
3.9 KiB
Python
Executable File
import unittest
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import random
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from migen import *
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from litedram.common import *
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from litedram.frontend.ecc import *
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from litex.gen.sim import *
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class TestECC(unittest.TestCase):
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def test_m_n(self):
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m, n = compute_m_n(15)
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self.assertEqual(m, 5)
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self.assertEqual(n, 20)
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def test_syndrome_positions(self):
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p_pos = compute_syndrome_positions(20)
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p_pos_ref = [1, 2, 4, 8, 16]
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self.assertEqual(p_pos, p_pos_ref)
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def test_data_positions(self):
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d_pos = compute_data_positions(20)
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d_pos_ref = [3, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 17, 18, 19, 20]
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self.assertEqual(d_pos, d_pos_ref)
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def test_cover_positions(self):
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c_pos_ref = {
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0 : [1, 3, 5, 7, 9, 11, 13, 15, 17, 19],
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1 : [2, 3, 6, 7, 10, 11, 14, 15, 18, 19],
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2 : [4, 5, 6, 7, 12, 13, 14, 15, 20],
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3 : [8, 9, 10, 11, 12, 13, 14, 15],
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4 : [16, 17, 18, 19, 20]
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}
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for i in range(5):
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c_pos = compute_cover_positions(20, 2**i)
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self.assertEqual(c_pos, c_pos_ref[i])
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def test_ecc(self, k=15):
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class DUT(Module):
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def __init__(self, k):
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m, n = compute_m_n(k)
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self.flip = Signal(n + 1)
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# # #
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self.submodules.encoder = ECCEncoder(k)
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self.submodules.decoder = ECCDecoder(k)
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self.comb += self.decoder.i.eq(self.encoder.o ^ self.flip)
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def generator(dut, k, nvalues, nerrors):
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dut.errors = 0
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prng = random.Random(42)
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yield dut.decoder.enable.eq(1)
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for i in range(nvalues):
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data = prng.randrange(2**k-1)
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yield dut.encoder.i.eq(data)
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# FIXME: error when fliping parity bit
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if nerrors == 1:
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flip_bit1 = (prng.randrange(len(dut.flip)-2) + 1)
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yield dut.flip.eq(1<<flip_bit1)
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elif nerrors == 2:
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flip_bit1 = (prng.randrange(len(dut.flip)-2) + 1)
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flip_bit2 = flip_bit1
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while flip_bit2 == flip_bit1:
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flip_bit2 = (prng.randrange(len(dut.flip)-2) + 1)
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yield dut.flip.eq((1<<flip_bit1) | (1<<flip_bit2))
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yield
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# if less than 2 errors, check data
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if nerrors < 2:
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if (yield dut.decoder.o) != data:
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dut.errors += 1
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# if 0 error, verify sec == 0 / ded == 0
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if nerrors == 0:
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if (yield dut.decoder.sec) != 0:
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dut.errors += 1
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if (yield dut.decoder.ded) != 0:
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dut.errors += 1
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# if 1 error, verify sec == 1 / dec == 0
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elif nerrors == 1:
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if (yield dut.decoder.sec) != 1:
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dut.errors += 1
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if (yield dut.decoder.ded) != 0:
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dut.errors += 1
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# if 2 errors, verify sec == 0 / ded == 1
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elif nerrors == 2:
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if (yield dut.decoder.sec) != 0:
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dut.errors += 1
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if (yield dut.decoder.ded) != 1:
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dut.errors += 1
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for i in range(3):
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dut = DUT(k)
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run_simulation(dut, generator(dut, k, 128, i))
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self.assertEqual(dut.errors, 0)
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def test_ecc_wrapper(self):
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# 32 bits + 8 bits ecc
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port_from = LiteDRAMNativePort("both", 24, 32*8)
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port_to = LiteDRAMNativePort("both", 24, 40*8)
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ecc = LiteDRAMNativePortECC(port_from, port_to)
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# 64 bits + 8 bits ecc
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port_from = LiteDRAMNativePort("both", 24, 64*8)
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port_to = LiteDRAMNativePort("both", 24, 72*8)
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ecc = LiteDRAMNativePortECC(port_from, port_to)
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