99 lines
2.8 KiB
Python
Executable File
99 lines
2.8 KiB
Python
Executable File
import unittest
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from litex.gen import *
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from litex.soc.interconnect.stream import *
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from litedram.common import PhySettings, LiteDRAMPort
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from litedram.core import *
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from litedram.modules import SDRAMModule
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from litedram.frontend.crossbar import LiteDRAMCrossbar
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from litedram.frontend.bist import _LiteDRAMBISTGenerator
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from litedram.frontend.bist import _LiteDRAMBISTChecker
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from litedram.frontend.adaptation import LiteDRAMPortCDC
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from litedram.phy.model import SDRAMPHYModel
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from test.common import *
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class SimModule(SDRAMModule):
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# geometry
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nbanks = 2
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nrows = 2048
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ncols = 2
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# timings
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tRP = 1
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tRCD = 1
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tWR = 1
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tWTR = 1
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tREFI = 1
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tRFC = 1
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class TB(Module):
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def __init__(self):
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# phy
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sdram_module = SimModule(1000, "1:1")
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phy_settings = PhySettings(
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memtype="SDR",
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dfi_databits=1*16,
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nphases=1,
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rdphase=0,
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wrphase=0,
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rdcmdphase=0,
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wrcmdphase=0,
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cl=2,
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read_latency=4,
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write_latency=0
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)
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self.submodules.sdrphy = SDRAMPHYModel(sdram_module,
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phy_settings,
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we_granularity=0)
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# controller
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self.submodules.controller = LiteDRAMController(
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phy_settings,
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sdram_module.geom_settings,
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sdram_module.timing_settings,
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ControllerSettings(with_refresh=False))
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self.comb += self.controller.dfi.connect(self.sdrphy.dfi)
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self.submodules.crossbar = LiteDRAMCrossbar(self.controller.interface,
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self.controller.nrowbits)
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# ports
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write_user_port = self.crossbar.get_port("write", cd="write")
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read_user_port = self.crossbar.get_port("read", cd="read")
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# generator / checker
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self.submodules.generator = _LiteDRAMBISTGenerator(write_user_port, True)
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self.submodules.checker = _LiteDRAMBISTChecker(read_user_port, True)
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def main_generator(dut):
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generator = BISTDriver(dut.generator)
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checker = BISTDriver(dut.checker)
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for i in range(16):
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yield
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# write
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yield from generator.reset()
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yield from generator.run(16, 16)
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# read (no errors)
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yield from checker.reset()
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yield from checker.run(16, 16)
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assert checker.errors == 0
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class TestBISTAsync(unittest.TestCase):
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def test(self):
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tb = TB()
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generators = {"sys" : [main_generator(tb)]}
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clocks = {"sys": 10,
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"write": 12,
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"read": 8}
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run_simulation(tb, generators, clocks, vcd_name="sim.vcd")
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self.assertEqual(dut.checker.error_count.status, 0)
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