234 lines
8.3 KiB
Python
Executable File
234 lines
8.3 KiB
Python
Executable File
import unittest
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import random
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from migen import *
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from litedram.common import *
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from litedram.frontend.axi import *
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from test.common import *
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from litex.gen.sim import *
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class Burst:
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def __init__(self, addr, type=burst_types["fixed"], len=0, size=0):
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self.addr = addr
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self.type = type
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self.len = len
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self.size = size
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def to_beats(self):
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r = []
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for i in range(self.len + 1):
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if self.type == burst_types["incr"]:
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offset = i*2**(self.size)
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r += [Beat(self.addr + offset)]
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elif self.type == burst_types["wrap"]:
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offset = (i*2**(self.size))%((2**self.size)*(self.len))
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r += [Beat(self.addr + offset)]
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else:
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r += [Beat(self.addr)]
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return r
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class Beat:
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def __init__(self, addr):
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self.addr = addr
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class Access(Burst):
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def __init__(self, addr, data, id, **kwargs):
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Burst.__init__(self, addr, **kwargs)
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self.data = data
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self.id = id
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class Write(Access):
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pass
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class Read(Access):
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pass
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class TestAXI(unittest.TestCase):
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def test_burst2beat(self):
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def bursts_generator(ax, bursts, valid_rand=50):
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prng = random.Random(42)
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for burst in bursts:
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yield ax.valid.eq(1)
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yield ax.addr.eq(burst.addr)
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yield ax.burst.eq(burst.type)
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yield ax.len.eq(burst.len)
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yield ax.size.eq(burst.size)
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while (yield ax.ready) == 0:
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yield
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yield ax.valid.eq(0)
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while prng.randrange(100) < valid_rand:
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yield
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yield
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@passive
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def beats_checker(ax, beats, ready_rand=50):
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self.errors = 0
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yield ax.ready.eq(0)
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prng = random.Random(42)
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for beat in beats:
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while ((yield ax.valid) and (yield ax.ready)) == 0:
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if prng.randrange(100) > ready_rand:
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yield ax.ready.eq(1)
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else:
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yield ax.ready.eq(0)
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yield
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ax_addr = (yield ax.addr)
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if ax_addr != beat.addr:
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self.errors += 1
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yield
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# dut
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ax_burst = stream.Endpoint(ax_description(32, 32))
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ax_beat = stream.Endpoint(ax_description(32, 32))
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dut = LiteDRAMAXIBurst2Beat(ax_burst, ax_beat)
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# generate dut input (bursts)
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prng = random.Random(42)
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bursts = []
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for i in range(32):
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bursts.append(Burst(prng.randrange(2**32), burst_types["fixed"], prng.randrange(255), log2_int(32//8)))
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bursts.append(Burst(prng.randrange(2**32), burst_types["incr"], prng.randrange(255), log2_int(32//8)))
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bursts.append(Burst(4, burst_types["wrap"], 4-1, log2_int(2)))
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# generate expexted dut output (beats for reference)
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beats = []
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for burst in bursts:
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beats += burst.to_beats()
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# simulation
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generators = [
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bursts_generator(ax_burst, bursts),
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beats_checker(ax_beat, beats)
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]
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run_simulation(dut, generators, vcd_name="burst2beat.vcd")
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self.assertEqual(self.errors, 0)
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def test_axi2native(self, with_random=True):
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def writes_cmd_generator(axi_port, writes):
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for write in writes:
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# send command
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yield axi_port.aw.valid.eq(1)
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yield axi_port.aw.addr.eq(write.addr<<2)
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yield axi_port.aw.burst.eq(write.type)
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yield axi_port.aw.len.eq(write.len)
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yield axi_port.aw.size.eq(write.size)
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yield axi_port.aw.id.eq(write.id)
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yield
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while (yield axi_port.aw.ready) == 0:
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yield
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yield axi_port.aw.valid.eq(0)
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def writes_data_generator(axi_port, writes):
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for write in writes:
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for i, data in enumerate(write.data):
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# send data
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yield axi_port.w.valid.eq(1)
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if (i == (len(write.data) - 1)):
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yield axi_port.w.last.eq(1)
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else:
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yield axi_port.w.last.eq(0)
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yield axi_port.w.data.eq(data)
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yield
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while (yield axi_port.w.ready) == 0:
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yield
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yield axi_port.w.valid.eq(0)
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def writes_response_generator(axi_port, writes):
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self.writes_id_errors = 0
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yield axi_port.b.ready.eq(1) # always accepting write response
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for write in writes:
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# wait response
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while (yield axi_port.b.valid) == 0:
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yield
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if (yield axi_port.b.id) != write.id:
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self.writes_id_errors += 1
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yield
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def reads_cmd_generator(axi_port, reads):
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for read in reads:
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# send command
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yield axi_port.ar.valid.eq(1)
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yield axi_port.ar.addr.eq(read.addr<<2)
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yield axi_port.ar.burst.eq(read.type)
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yield axi_port.ar.len.eq(read.len)
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yield axi_port.ar.size.eq(read.size)
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yield axi_port.ar.id.eq(read.id)
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yield
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while (yield axi_port.ar.ready) == 0:
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yield
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yield axi_port.ar.valid.eq(0)
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def reads_response_data_generator(axi_port, reads):
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self.reads_data_errors = 0
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self.reads_id_errors = 0
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self.reads_last_errors = 0
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yield axi_port.r.ready.eq(1) # always accepting read response
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yield
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for read in reads:
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for i, data in enumerate(read.data):
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# wait data / response
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while (yield axi_port.r.valid) == 0:
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yield
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if (yield axi_port.r.data) != data:
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self.reads_data_errors += 1
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if (yield axi_port.r.id) != read.id:
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self.reads_id_errors += 1
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if i == (len(read.data) - 1):
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if (yield axi_port.r.last) != 1:
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self.reads_last_errors += 1
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else:
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if (yield axi_port.r.last) != 0:
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self.reads_last_errors += 1
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yield
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# dut
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axi_port = LiteDRAMAXIPort(32, 32, 8)
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dram_port = LiteDRAMNativePort("both", 32, 32)
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dut = LiteDRAMAXI2Native(axi_port, dram_port)
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mem = DRAMMemory(32, 128)
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# generate writes/reads
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prng = random.Random(42)
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writes = []
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for i in range(16):
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if with_random:
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# incrementing addr, random data &id
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writes.append(Write(i, [prng.randrange(2**32) for _ in range(i+1)], prng.randrange(2**8), type=0b00, len=i))
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else:
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# incrementing addr, data & id (debug)
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writes.append(Write(i, [i for _ in range(i+1)], i, type=0b00, len=i))
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reads = []
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for i in range(16):
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if with_random:
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# incrementing addr, written data, random id
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reads.append(Read(i, writes[i].data, prng.randrange(2**8), type=0b00, len=len(writes[i].data)-1))
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else:
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# incrementing addr, written data, incrementing id (debug)
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reads.append(Read(i, writes[i].data, i, type=0b00, len=len(writes[i].data)-1))
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# simulation
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generators = [
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writes_cmd_generator(axi_port, writes),
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writes_data_generator(axi_port, writes),
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writes_response_generator(axi_port, writes),
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reads_cmd_generator(axi_port, reads),
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reads_response_data_generator(axi_port, reads),
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mem.read_handler(dram_port),
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mem.write_handler(dram_port)
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]
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run_simulation(dut, generators, vcd_name="axi2native.vcd")
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#mem.show_content()
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self.assertEqual(self.writes_id_errors, 0)
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self.assertEqual(self.reads_data_errors, 0)
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self.assertEqual(self.reads_id_errors, 0)
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self.assertEqual(self.reads_last_errors, 0)
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