320 lines
11 KiB
Python
320 lines
11 KiB
Python
#
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# This file is part of LiteDRAM.
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#
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# Copyright (c) 2019-2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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import random
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from migen import *
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from litex.soc.interconnect.stream import *
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from litedram.common import LiteDRAMNativeWritePort
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from litedram.common import LiteDRAMNativeReadPort
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from litedram.frontend.fifo import LiteDRAMFIFO, _LiteDRAMFIFOCtrl
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from litedram.frontend.fifo import _LiteDRAMFIFOWriter, _LiteDRAMFIFOReader
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from test.common import *
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class FIFODUT(Module):
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def __init__(self, base, depth, data_width=8, address_width=32, with_bypass=False):
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port_data_width = data_width if not with_bypass else 4*data_width
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self.write_port = LiteDRAMNativeWritePort(address_width=32, data_width=port_data_width)
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self.read_port = LiteDRAMNativeReadPort(address_width=32, data_width=port_data_width)
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self.submodules.fifo = LiteDRAMFIFO(
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data_width = data_width,
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base = base,
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depth = depth,
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write_port = self.write_port,
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read_port = self.read_port,
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with_bypass = with_bypass
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)
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margin = 8
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self.memory = DRAMMemory(port_data_width, base + depth + margin)
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def write(self, data):
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yield self.fifo.sink.valid.eq(1)
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yield self.fifo.sink.data.eq(data)
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yield
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while not (yield self.fifo.sink.ready):
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yield
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yield self.fifo.sink.valid.eq(0)
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def read(self):
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while not (yield self.fifo.source.valid):
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yield
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yield self.fifo.source.ready.eq(1)
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data = (yield self.fifo.source.data)
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yield
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yield self.fifo.source.ready.eq(0)
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yield
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return data
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class TestFIFO(unittest.TestCase):
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# _LiteDRAMFIFOCtrl ----------------------------------------------------------------------------
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def test_fifo_ctrl_address_changes(self):
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# Verify FIFOCtrl address changes.
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dut = _LiteDRAMFIFOCtrl(base=0, depth=16)
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def main_generator():
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self.assertEqual((yield dut.write_address), 0)
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self.assertEqual((yield dut.read_address), 0)
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# Write address
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yield dut.write.eq(1)
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yield
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# Write_address gets updated 1 cycle later
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for i in range(24 - 1):
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self.assertEqual((yield dut.write_address), i % 16)
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yield
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yield dut.write.eq(0)
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yield
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self.assertEqual((yield dut.write_address), 24 % 16)
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# Read address
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yield dut.read.eq(1)
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yield
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for i in range(24 - 1):
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self.assertEqual((yield dut.read_address), i % 16)
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yield
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yield dut.read.eq(0)
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yield
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self.assertEqual((yield dut.read_address), 24 % 16)
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run_simulation(dut, main_generator())
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def test_fifo_ctrl_level_changes(self):
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# Verify FIFOCtrl level changes.
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dut = _LiteDRAMFIFOCtrl(base=0, depth=16)
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def main_generator():
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self.assertEqual((yield dut.level), 0)
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def check_level_diff(write, read, diff):
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level = (yield dut.level)
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yield dut.write.eq(write)
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yield dut.read.eq(read)
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yield
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yield dut.write.eq(0)
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yield dut.read.eq(0)
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yield
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self.assertEqual((yield dut.level), level + diff)
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check_level_diff(write=1, read=0, diff=+1)
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check_level_diff(write=1, read=0, diff=+1)
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check_level_diff(write=1, read=1, diff=+0)
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check_level_diff(write=1, read=1, diff=+0)
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check_level_diff(write=0, read=1, diff=-1)
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check_level_diff(write=0, read=1, diff=-1)
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run_simulation(dut, main_generator())
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# _LiteDRAMFIFOWriter --------------------------------------------------------------------------
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def fifo_writer_test(self, depth, sequence_len, consume=False):
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class DUT(Module):
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def __init__(self):
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self.port = LiteDRAMNativeWritePort(address_width=32, data_width=32)
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ctrl = _LiteDRAMFIFOCtrl(base=8, depth=depth)
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self.submodules.ctrl = ctrl
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writer = _LiteDRAMFIFOWriter(data_width=32, port=self.port, ctrl=ctrl)
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self.submodules.writer = writer
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self.memory = DRAMMemory(32, 128)
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assert 8 + sequence_len <= len(self.memory.mem)
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write_data = [seed_to_data(i) for i in range(sequence_len)]
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def generator(dut):
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for data in write_data:
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yield dut.writer.sink.valid.eq(1)
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yield dut.writer.sink.data.eq(data)
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yield
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while (yield dut.writer.sink.ready) == 0:
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yield
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yield dut.writer.sink.valid.eq(0)
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if consume:
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yield dut.ctrl.read.eq(1)
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for _ in range(16):
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yield
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dut = DUT()
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generators = [
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generator(dut),
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dut.memory.write_handler(dut.port),
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timeout_generator(1500),
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]
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run_simulation(dut, generators)
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mem_expected = [0] * len(dut.memory.mem)
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for i, data in enumerate(write_data):
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mem_expected[8 + i%depth] = data
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self.assertEqual(dut.memory.mem, mem_expected)
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def test_fifo_writer_sequence(self):
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# Verify simple FIFOWriter sequence.
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self.fifo_writer_test(sequence_len=48, depth=64)
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def test_fifo_writer_stops_when_full(self):
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# Verify FIFOWriter won't continue writing if noone reads the data.
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with self.assertRaises(TimeoutError):
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self.fifo_writer_test(sequence_len=48, depth=32)
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def test_fifo_writer_address_wraps(self):
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# Verify FIFOWriter address wraps.
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self.fifo_writer_test(sequence_len=48, depth=32, consume=True)
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# _LiteDRAMFIFOReader --------------------------------------------------------------------------
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def fifo_reader_test(self, depth, sequence_len, inital_writes=0):
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memory_data = [seed_to_data(i) for i in range(128)]
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read_data = []
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class DUT(Module):
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def __init__(self):
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self.port = LiteDRAMNativeReadPort(address_width=32, data_width=32)
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ctrl = _LiteDRAMFIFOCtrl(base=8, depth=depth)
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reader = _LiteDRAMFIFOReader(data_width=32, port=self.port, ctrl=ctrl)
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self.submodules.ctrl = ctrl
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self.submodules.reader = reader
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self.memory = DRAMMemory(32, len(memory_data), init=memory_data)
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assert 8 + sequence_len <= len(self.memory.mem)
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def reader(dut):
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# Fake writing to fifo
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yield dut.ctrl.write.eq(1)
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for _ in range(inital_writes):
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yield
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yield dut.ctrl.write.eq(0)
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yield
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for _ in range(sequence_len):
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# Fake single write
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yield dut.ctrl.write.eq(1)
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yield
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yield dut.ctrl.write.eq(0)
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while (yield dut.reader.source.valid) == 0:
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yield
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read_data.append((yield dut.reader.source.data))
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yield dut.reader.source.ready.eq(1)
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yield
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yield dut.reader.source.ready.eq(0)
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yield
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dut = DUT()
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generators = [
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reader(dut),
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dut.memory.read_handler(dut.port),
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timeout_generator(1500),
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]
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run_simulation(dut, generators)
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read_data_expected = [memory_data[8 + i%depth] for i in range(sequence_len)]
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self.assertEqual(read_data, read_data_expected)
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def test_fifo_reader_sequence(self):
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# Verify simple FIFOReader sequence.
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self.fifo_reader_test(sequence_len=48, depth=64)
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def test_fifo_reader_address_wraps(self):
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# Verify FIFOReader sequence with address wraps.
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self.fifo_reader_test(sequence_len=48, depth=32)
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# LiteDRAMFIFO ---------------------------------------------------------------------------------
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def fifo_continuous_stream_short_test(self, with_bypass):
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# Verify FIFO operation with continuous writes and reads without wrapping
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def generator(dut):
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for i in range(64):
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yield from dut.write(10 + i)
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def checker(dut):
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for i in range(64):
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data = (yield from dut.read())
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self.assertEqual(data, 10 + i)
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dut = FIFODUT(base=16, depth=128, with_bypass=with_bypass)
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generators = [
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generator(dut),
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checker(dut),
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dut.memory.write_handler(dut.write_port),
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dut.memory.read_handler(dut.read_port),
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timeout_generator(1500),
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]
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run_simulation(dut, generators)
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def test_fifo_continuous_stream_short(self):
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self.fifo_continuous_stream_short_test(with_bypass=False)
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def test_fifo_continuous_stream_short_with_bypass(self):
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self.fifo_continuous_stream_short_test(with_bypass=True)
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def fifo_continuous_stream_long_test(self, with_bypass):
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# Verify FIFO operation with continuous writes and reads with wrapping
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def generator(dut):
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for i in range(64):
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yield from dut.write(10 + i)
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def checker(dut):
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for i in range(64):
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data = (yield from dut.read())
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self.assertEqual(data, 10 + i)
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dut = FIFODUT(base=16, depth=32, with_bypass=with_bypass)
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generators = [
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generator(dut),
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checker(dut),
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dut.memory.write_handler(dut.write_port),
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dut.memory.read_handler(dut.read_port),
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timeout_generator(1500),
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]
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run_simulation(dut, generators)
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def test_fifo_continuous_stream_long(self):
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self.fifo_continuous_stream_long_test(with_bypass=False)
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def test_fifo_continuous_stream_long_with_bypass(self):
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self.fifo_continuous_stream_long_test(with_bypass=True)
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def fifo_delayed_reader_test(self, with_bypass):
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# Verify FIFO works correctly when reader starts reading only after writer is full
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def generator(dut):
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for i in range(128):
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yield from dut.write(10 + i)
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def checker(dut):
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# Wait until both the internal writer FIFO and our in-memory FIFO are full
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for i in range(256):
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yield
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for i in range(128):
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data = (yield from dut.read())
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self.assertEqual(data, 10 + i)
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for i in range(32):
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yield
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dut = FIFODUT(base=16, depth=32, with_bypass=with_bypass)
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generators = [
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generator(dut),
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checker(dut),
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dut.memory.write_handler(dut.write_port),
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dut.memory.read_handler(dut.read_port),
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timeout_generator(1500),
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]
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run_simulation(dut, generators)
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def test_fifo_delayed_reader(self):
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self.fifo_delayed_reader_test(with_bypass=False)
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def test_fifo_delayed_reader_with_bypass(self):
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self.fifo_delayed_reader_test(with_bypass=True) |