123 lines
5.8 KiB
Python
123 lines
5.8 KiB
Python
#
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# This file is part of LiteDRAM.
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#
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# Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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from migen import *
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from litex.gen.sim import run_simulation
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from litex.soc.interconnect import wishbone
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from litedram.frontend.wishbone import LiteDRAMWishbone2Native
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from litedram.common import LiteDRAMNativePort
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from test.common import DRAMMemory, MemoryTestDataMixin
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class TestWishbone(MemoryTestDataMixin, unittest.TestCase):
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def wishbone_readback_test(self, pattern, mem_expected, wishbone, port, base_address=0):
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class DUT(Module):
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def __init__(self):
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self.port = port
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self.wb = wishbone
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self.submodules += LiteDRAMWishbone2Native(
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wishbone = self.wb,
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port = self.port,
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base_address = base_address)
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self.mem = DRAMMemory(port.data_width, len(mem_expected))
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def main_generator(dut):
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for adr, data in pattern:
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yield from dut.wb.write(adr, data)
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data_r = (yield from dut.wb.read(adr))
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self.assertEqual(data_r, data)
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dut = DUT()
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generators = [
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main_generator(dut),
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dut.mem.write_handler(dut.port),
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dut.mem.read_handler(dut.port),
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]
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run_simulation(dut, generators, vcd_name='sim.vcd')
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self.assertEqual(dut.mem.mem, mem_expected)
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def test_wishbone_8bit(self):
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# Verify Wishbone with 8-bit data width.
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data = self.pattern_test_data["8bit"]
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wb = wishbone.Interface(adr_width=30, data_width=8)
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port = LiteDRAMNativePort("both", address_width=30, data_width=8)
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self.wishbone_readback_test(data["pattern"], data["expected"], wb, port)
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def test_wishbone_32bit(self):
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# Verify Wishbone with 32-bit data width.
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data = self.pattern_test_data["32bit"]
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wb = wishbone.Interface(adr_width=30, data_width=32)
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port = LiteDRAMNativePort("both", address_width=30, data_width=32)
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self.wishbone_readback_test(data["pattern"], data["expected"], wb, port)
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def test_wishbone_64bit(self):
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# Verify Wishbone with 64-bit data width.
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data = self.pattern_test_data["64bit"]
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wb = wishbone.Interface(adr_width=30, data_width=64)
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port = LiteDRAMNativePort("both", address_width=30, data_width=64)
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self.wishbone_readback_test(data["pattern"], data["expected"], wb, port)
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def test_wishbone_64bit_to_32bit(self):
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# Verify Wishbone with 64-bit data width down-converted to 32-bit data width.
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data = self.pattern_test_data["64bit_to_32bit"]
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wb = wishbone.Interface(adr_width=30, data_width=64)
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port = LiteDRAMNativePort("both", address_width=30, data_width=32)
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self.wishbone_readback_test(data["pattern"], data["expected"], wb, port)
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def test_wishbone_32bit_to_8bit(self):
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# Verify Wishbone with 32-bit data width down-converted to 8-bit data width.
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data = self.pattern_test_data["32bit_to_8bit"]
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wb = wishbone.Interface(adr_width=30, data_width=32)
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port = LiteDRAMNativePort("both", address_width=30, data_width=8)
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self.wishbone_readback_test(data["pattern"], data["expected"], wb, port)
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def test_wishbone_8bit_to_32bit(self):
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# Verify Wishbone with 8-bit data width up-converted to 32-bit data width.
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data = self.pattern_test_data["8bit_to_32bit"]
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wb = wishbone.Interface(adr_width=30, data_width=8)
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port = LiteDRAMNativePort("both", address_width=30, data_width=32)
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self.wishbone_readback_test(data["pattern"], data["expected"], wb, port)
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def test_wishbone_32bit_to_64bit(self):
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# Verify Wishbone with 32-bit data width up-converted to 64-bit data width.
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data = self.pattern_test_data["32bit_to_64bit"]
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wb = wishbone.Interface(adr_width=30, data_width=32)
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port = LiteDRAMNativePort("both", address_width=30, data_width=64)
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self.wishbone_readback_test(data["pattern"], data["expected"], wb, port)
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def test_wishbone_32bit_base_address(self):
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# Verify Wishbone with 32-bit data width and non-zero base address.
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data = self.pattern_test_data["32bit"]
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wb = wishbone.Interface(adr_width=30, data_width=32)
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port = LiteDRAMNativePort("both", address_width=30, data_width=32)
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origin = 0x10000000
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# add offset (in data words)
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pattern = [(adr + origin//(32//8), data) for adr, data in data["pattern"]]
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self.wishbone_readback_test(pattern, data["expected"], wb, port, base_address=origin)
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def test_wishbone_64bit_to_32bit_base_address(self):
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# Verify Wishbone with 64-bit data width down-converted to 32-bit data width and non-zero base address.
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data = self.pattern_test_data["64bit_to_32bit"]
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wb = wishbone.Interface(adr_width=30, data_width=64)
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port = LiteDRAMNativePort("both", address_width=30, data_width=32)
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origin = 0x10000000
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pattern = [(adr + origin//(64//8), data) for adr, data in data["pattern"]]
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self.wishbone_readback_test(pattern, data["expected"], wb, port, base_address=origin)
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def test_wishbone_32bit_to_8bit_base_address(self):
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# Verify Wishbone with 32-bit data width down-converted to 8-bit data width and non-zero base address.
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data = self.pattern_test_data["32bit_to_8bit"]
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wb = wishbone.Interface(adr_width=30, data_width=32)
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port = LiteDRAMNativePort("both", address_width=30, data_width=8)
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origin = 0x10000000
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pattern = [(adr + origin//(32//8), data) for adr, data in data["pattern"]]
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self.wishbone_readback_test(pattern, data["expected"], wb, port, base_address=origin)
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