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litedram/test
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Tim 'mithro' Ansell da144f41d4 bist: Refactoring test bench. 
Move a bunch of common code into common.py
2016-12-17 14:09:50 +01:00
..
__init__.py update code, start bankmachine refactoring and remove old code (will be rewritten) 2015-09-15 10:22:39 +02:00
bist_async_tb.py bist: Refactoring test bench. 2016-12-17 14:09:50 +01:00
bist_tb.py bist: Refactoring test bench. 2016-12-17 14:09:50 +01:00
common.py bist: Refactoring test bench. 2016-12-17 14:09:50 +01:00
downconverter_tb.py frontend: introduce mode on ports: write, read or both 2016-06-15 17:51:46 +02:00
Makefile test: add upconverter_tb and some fixes 2016-05-24 21:14:49 +02:00
upconverter_tb.py frontend/adaptation: implement LiteDRAMReadPortUpConverter correctly 2016-06-15 23:57:16 +02:00