64 lines
1.7 KiB
Python
Executable File
64 lines
1.7 KiB
Python
Executable File
import unittest
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import random
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from migen import *
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from litex.soc.interconnect.stream import *
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from litedram.common import LiteDRAMWritePort, LiteDRAMReadPort
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from litedram.frontend.bist import _LiteDRAMBISTGenerator
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from litedram.frontend.bist import _LiteDRAMBISTChecker
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from test.common import *
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class DUT(Module):
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def __init__(self):
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self.write_port = LiteDRAMWritePort(aw=32, dw=32)
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self.read_port = LiteDRAMReadPort(aw=32, dw=32)
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self.submodules.generator = _LiteDRAMBISTGenerator(self.write_port, True)
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self.submodules.checker = _LiteDRAMBISTChecker(self.read_port, True)
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def main_generator(dut, mem):
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generator = BISTDriver(dut.generator)
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checker = BISTDriver(dut.checker)
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# write
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yield from generator.reset()
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yield from generator.run(16, 64)
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# read (no errors)
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yield from checker.reset()
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yield from checker.run(16, 64)
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assert checker.errors == 0
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# corrupt memory (using generator)
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yield from generator.reset()
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yield from generator.run(16 + 60, 64)
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# read (4 errors)
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yield from checker.reset()
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yield from checker.run(16, 64)
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assert checker.errors == 4
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# read (no errors)
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yield from checker.reset()
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yield from checker.run(16 + 60, 64)
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assert checker.errors == 0
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class TestBIST(unittest.TestCase):
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def test(self):
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dut = DUT()
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mem = DRAMMemory(32, 128)
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generators = {
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"sys" : [
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main_generator(dut, mem),
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mem.write_generator(dut.write_port),
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mem.read_generator(dut.read_port)
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]
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}
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clocks = {"sys": 10}
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run_simulation(dut, generators, clocks, vcd_name="sim.vcd")
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