134 lines
3.4 KiB
Python
Executable File
134 lines
3.4 KiB
Python
Executable File
#!/usr/bin/env python3
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import random
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from litex.gen import *
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from litex.soc.interconnect.stream import *
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from litedram.common import LiteDRAMWritePort, LiteDRAMReadPort
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from litedram.frontend.bist import LiteDRAMBISTGenerator
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from litedram.frontend.bist import LiteDRAMBISTChecker
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from test.common import DRAMMemory
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class TB(Module):
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def __init__(self):
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self.write_port = LiteDRAMWritePort(aw=32, dw=32)
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self.read_port = LiteDRAMReadPort(aw=32, dw=32)
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self.submodules.generator = LiteDRAMBISTGenerator(self.write_port)
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self.submodules.checker = LiteDRAMBISTChecker(self.read_port)
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def togglereset(module):
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resig = module.reset.re
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# Check that reset isn't set
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reval = yield resig
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assert not reval, reval
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# Toggle the reset
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yield resig.eq(1)
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yield
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yield resig.eq(0)
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yield # Takes 3 clock cycles for the reset to have an effect
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yield
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yield
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yield
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yield
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yield
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# Check some initial conditions are correct after reset.
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started = yield module.core.started
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assert started == 0, started
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done = yield module.done.status
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assert not done, done
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def main_generator(dut, mem):
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# Populate memory with random data
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random.seed(0)
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for i in range(0, len(mem.mem)):
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mem.mem[i] = random.randint(0, 2**mem.width)
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# write
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yield from togglereset(dut.generator)
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yield dut.generator.base.storage.eq(16)
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yield dut.generator.length.storage.eq(64)
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for i in range(8):
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yield
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yield dut.generator.start.re.eq(1)
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yield
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yield dut.generator.start.re.eq(0)
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for i in range(8):
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yield
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while((yield dut.generator.done.status) == 0):
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yield
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done = yield dut.generator.done.status
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assert done, done
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# read with no errors
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yield from togglereset(dut.checker)
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errors = yield dut.checker.error_count.status
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assert errors == 0, errors
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yield dut.checker.base.storage.eq(16)
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yield dut.checker.length.storage.eq(64)
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for i in range(8):
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yield
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yield dut.checker.start.re.eq(1)
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yield
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yield dut.checker.start.re.eq(0)
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for i in range(8):
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yield
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while((yield dut.checker.done.status) == 0):
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yield
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done = yield dut.checker.done.status
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assert done, done
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errors = yield dut.checker.error_count.status
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assert errors == 0, errors
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yield
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yield
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# read with one error
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yield from togglereset(dut.checker)
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errors = yield dut.checker.error_count.status
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assert errors == 0, errors
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assert mem.mem[20] != 0, mem.mem[20]
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mem.mem[20] = 0 # Make position 20 an error
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yield dut.checker.base.storage.eq(16)
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yield dut.checker.length.storage.eq(64)
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for i in range(8):
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yield
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yield dut.checker.start.re.eq(1)
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yield
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yield dut.checker.start.re.eq(0)
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for i in range(8):
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yield
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while((yield dut.checker.done.status) == 0):
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yield
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done = yield dut.checker.done.status
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assert done, done
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errors = yield dut.checker.error_count.status
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assert errors == 1, errors
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yield
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yield
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if __name__ == "__main__":
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tb = TB()
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mem = DRAMMemory(32, 128)
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generators = {
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"sys" : [main_generator(tb, mem),
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mem.write_generator(tb.write_port),
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mem.read_generator(tb.read_port)]
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}
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clocks = {"sys": 10}
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run_simulation(tb, generators, clocks, vcd_name="sim.vcd")
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