Anton Blanchard e0cf7d579e phy/ecp5ddrphy: set rtt_nom/rtt_wr/ron from YAML config		2021-10-03 20:02:51 +11:00
..
core	Merge pull request #238 from antmicro/jboc/refresh-all-banks	2021-03-31 08:50:25 +02:00
frontend	frontend/fifo: Simplify level on _LiteDRAMFIFOCtrl, fix ctrl.write on _LiteDRAMFIFOWriter.	2021-09-24 19:34:55 +02:00
phy	phy/s7ddrphy: Only add +1 to CL for DDR3 (thanks gsomlo).	2021-09-15 08:43:31 +02:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	phy: update PHYs to set capabilities, delays/bitslips in PhySettings	2021-08-04 12:30:56 +02:00
dfii.py	add SPDX License identifier to header and specify file is part of LiteDRAM.	2020-08-23 15:52:08 +02:00
gen.py	phy/ecp5ddrphy: set rtt_nom/rtt_wr/ron from YAML config	2021-10-03 20:02:51 +11:00
init.py	phy: update PHYs to set capabilities, delays/bitslips in PhySettings	2021-08-04 12:30:56 +02:00
modules.py	modules/IS43TR16512B: Review timings, add 800/1066/1333 speedgrades.	2021-09-30 17:56:40 +02:00