litedram/litedram
Florent Kermarrec eddd6e4eaf modules/init: add DDR4 fine refresh mode support: x1, x2 and x4 (x1=previous and default behavior) 2019-12-03 12:20:32 +01:00
..
core core/controller: cleanup ControllerSettings 2019-12-03 12:16:50 +01:00
frontend frontend/wishbone: remove LiteDRAMWishbone2AXI (can be replaced with LiteX's Wishbone2AXILite) 2019-11-30 11:06:41 +01:00
phy global: improve presentation/readability 2019-11-30 10:53:11 +01:00
__init__.py update code, start bankmachine refactoring and remove old code (will be rewritten) 2015-09-15 10:22:39 +02:00
common.py global: improve presentation/readability 2019-11-30 10:53:11 +01:00
dfii.py global: improve presentation/readability 2019-11-30 10:53:11 +01:00
gen.py global: improve presentation/readability 2019-11-30 10:53:11 +01:00
init.py modules/init: add DDR4 fine refresh mode support: x1, x2 and x4 (x1=previous and default behavior) 2019-12-03 12:20:32 +01:00
modules.py modules/init: add DDR4 fine refresh mode support: x1, x2 and x4 (x1=previous and default behavior) 2019-12-03 12:20:32 +01:00