239 lines
9.9 KiB
Python
239 lines
9.9 KiB
Python
# This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
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# License: BSD
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import unittest
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from migen import *
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from litex.soc.interconnect import stream
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from litedram.common import *
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from litedram.phy import dfi
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from litedram.core.multiplexer import _Steerer
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from litedram.core.multiplexer import STEER_NOP, STEER_CMD, STEER_REQ, STEER_REFRESH
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from test.common import CmdRequestRWDriver
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class SteererDUT(Module):
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def __init__(self, nranks, dfi_databits, nphases):
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a, ba = 13, 3
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nop = Record(cmd_request_layout(a=a, ba=ba))
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choose_cmd = stream.Endpoint(cmd_request_rw_layout(a=a, ba=ba))
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choose_req = stream.Endpoint(cmd_request_rw_layout(a=a, ba=ba))
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refresher_cmd = stream.Endpoint(cmd_request_rw_layout(a=a, ba=ba))
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self.commands = [nop, choose_cmd, choose_req, refresher_cmd]
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self.dfi = dfi.Interface(addressbits=a, bankbits=ba, nranks=nranks, databits=dfi_databits,
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nphases=nphases)
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self.submodules.steerer = _Steerer(self.commands, self.dfi)
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# nop is not an endpoint and does not have is_* signals
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self.drivers = [CmdRequestRWDriver(req, i, ep_layout=i != 0, rw_layout=i != 0)
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for i, req in enumerate(self.commands)]
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class TestSteerer(unittest.TestCase):
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def test_nop_not_valid(self):
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# If NOP is selected then there should be no command selected on cas/ras/we
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def main_generator(dut):
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# nop on both phases
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yield dut.steerer.sel[0].eq(STEER_NOP)
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yield dut.steerer.sel[1].eq(STEER_NOP)
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yield from dut.drivers[0].nop()
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yield
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for i in range(2):
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cas_n = (yield dut.dfi.phases[i].cas_n)
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ras_n = (yield dut.dfi.phases[i].ras_n)
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we_n = (yield dut.dfi.phases[i].we_n)
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self.assertEqual((cas_n, ras_n, we_n), (1, 1, 1))
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dut = SteererDUT(nranks=2, dfi_databits=16, nphases=2)
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run_simulation(dut, main_generator(dut))
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def test_connect_only_if_valid_and_ready(self):
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# Commands should be connected to phases only if they are valid & ready
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def main_generator(dut):
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# set possible requests
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yield from dut.drivers[STEER_NOP].nop()
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yield from dut.drivers[STEER_CMD].activate()
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yield from dut.drivers[STEER_REQ].write()
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yield from dut.drivers[STEER_REFRESH].refresh()
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# set how phases are steered
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yield dut.steerer.sel[0].eq(STEER_CMD)
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yield dut.steerer.sel[1].eq(STEER_NOP)
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yield
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yield
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def check(is_ready):
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# cmd on phase 0 should be STEER_CMD=activate
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p = dut.dfi.phases[0]
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self.assertEqual((yield p.bank), STEER_CMD)
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self.assertEqual((yield p.address), STEER_CMD)
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if is_ready:
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self.assertEqual((yield p.cas_n), 1)
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self.assertEqual((yield p.ras_n), 0)
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self.assertEqual((yield p.we_n), 1)
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else: # not steered
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self.assertEqual((yield p.cas_n), 1)
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self.assertEqual((yield p.ras_n), 1)
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self.assertEqual((yield p.we_n), 1)
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# nop on phase 1 should be STEER_NOP
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p = dut.dfi.phases[1]
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self.assertEqual((yield p.cas_n), 1)
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self.assertEqual((yield p.ras_n), 1)
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self.assertEqual((yield p.we_n), 1)
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yield from check(is_ready=False)
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yield dut.commands[STEER_CMD].ready.eq(1)
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yield
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yield
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yield from check(is_ready=True)
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dut = SteererDUT(nranks=2, dfi_databits=16, nphases=2)
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run_simulation(dut, main_generator(dut))
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def test_no_decode_ba_signle_rank(self):
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# With a single rank the whole `ba` signal is bank address
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def main_generator(dut):
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yield from dut.drivers[STEER_NOP].nop()
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yield from dut.drivers[STEER_REQ].write()
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yield from dut.drivers[STEER_REFRESH].refresh()
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# all the bits are for bank
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dut.drivers[STEER_CMD].bank = 0b110
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yield from dut.drivers[STEER_CMD].activate()
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yield dut.commands[STEER_CMD].ready.eq(1)
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# set how phases are steered
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yield dut.steerer.sel[0].eq(STEER_NOP)
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yield dut.steerer.sel[1].eq(STEER_CMD)
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yield
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yield
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p = dut.dfi.phases[1]
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self.assertEqual((yield p.cas_n), 1)
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self.assertEqual((yield p.ras_n), 0)
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self.assertEqual((yield p.we_n), 1)
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self.assertEqual((yield p.address), STEER_CMD)
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self.assertEqual((yield p.bank), 0b110)
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self.assertEqual((yield p.cs_n), 0)
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dut = SteererDUT(nranks=1, dfi_databits=16, nphases=2)
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run_simulation(dut, main_generator(dut))
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def test_decode_ba_multiple_ranks(self):
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# With multiple ranks `ba` signal should be split into bank and chip select
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def main_generator(dut):
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yield from dut.drivers[STEER_NOP].nop()
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yield from dut.drivers[STEER_REQ].write()
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yield from dut.drivers[STEER_REFRESH].refresh()
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# set how phases are steered
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yield dut.steerer.sel[0].eq(STEER_NOP)
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yield dut.steerer.sel[1].eq(STEER_CMD)
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variants = [
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# ba, phase.bank, phase.cs_n
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(0b110, 0b10, 0b01), # rank=1 -> cs=0b10 -> cs_n=0b01
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(0b101, 0b01, 0b01), # rank=1 -> cs=0b10 -> cs_n=0b01
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(0b001, 0b01, 0b10), # rank=0 -> cs=0b01 -> cs_n=0b10
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]
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for ba, phase_bank, phase_cs_n in variants:
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with self.subTest(ba=ba):
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# 1 bit for rank, 2 bits for bank
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dut.drivers[STEER_CMD].bank = ba
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yield from dut.drivers[STEER_CMD].activate()
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yield dut.commands[STEER_CMD].ready.eq(1)
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yield
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yield
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p = dut.dfi.phases[1]
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self.assertEqual((yield p.cas_n), 1)
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self.assertEqual((yield p.ras_n), 0)
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self.assertEqual((yield p.we_n), 1)
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self.assertEqual((yield p.bank), phase_bank)
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self.assertEqual((yield p.cs_n), phase_cs_n)
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dut = SteererDUT(nranks=2, dfi_databits=16, nphases=2)
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run_simulation(dut, main_generator(dut))
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def test_select_all_ranks_on_refresh(self):
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# When refresh command is on first phase, all ranks should be selected
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def main_generator(dut):
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yield from dut.drivers[STEER_NOP].nop()
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yield from dut.drivers[STEER_REQ].write()
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yield from dut.drivers[STEER_CMD].activate()
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# set how phases are steered
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yield dut.steerer.sel[0].eq(STEER_REFRESH)
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yield dut.steerer.sel[1].eq(STEER_NOP)
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variants = [
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# ba, phase.bank, phase.cs_n (always all enabled)
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(0b110, 0b10, 0b00),
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(0b101, 0b01, 0b00),
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(0b001, 0b01, 0b00),
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]
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for ba, phase_bank, phase_cs_n in variants:
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with self.subTest(ba=ba):
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# 1 bit for rank, 2 bits for bank
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dut.drivers[STEER_REFRESH].bank = ba
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yield from dut.drivers[STEER_REFRESH].refresh()
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yield dut.commands[STEER_REFRESH].ready.eq(1)
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yield
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yield
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p = dut.dfi.phases[0]
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self.assertEqual((yield p.cas_n), 0)
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self.assertEqual((yield p.ras_n), 0)
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self.assertEqual((yield p.we_n), 1)
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self.assertEqual((yield p.bank), phase_bank)
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self.assertEqual((yield p.cs_n), phase_cs_n)
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dut = SteererDUT(nranks=2, dfi_databits=16, nphases=2)
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run_simulation(dut, main_generator(dut))
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def test_reset_n_high(self):
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# reset_n should be 1 for all phases at all times
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def main_generator(dut):
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yield dut.steerer.sel[0].eq(STEER_CMD)
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yield dut.steerer.sel[1].eq(STEER_NOP)
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yield
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self.assertEqual((yield dut.dfi.phases[0].reset_n), 1)
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self.assertEqual((yield dut.dfi.phases[1].reset_n), 1)
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self.assertEqual((yield dut.dfi.phases[2].reset_n), 1)
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self.assertEqual((yield dut.dfi.phases[3].reset_n), 1)
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dut = SteererDUT(nranks=2, dfi_databits=16, nphases=4)
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run_simulation(dut, main_generator(dut))
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def test_cke_high_all_ranks(self):
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# cke should be 1 for all phases and ranks at all times
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def main_generator(dut):
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yield dut.steerer.sel[0].eq(STEER_CMD)
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yield dut.steerer.sel[1].eq(STEER_NOP)
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yield
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self.assertEqual((yield dut.dfi.phases[0].cke), 0b11)
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self.assertEqual((yield dut.dfi.phases[1].cke), 0b11)
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self.assertEqual((yield dut.dfi.phases[2].cke), 0b11)
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self.assertEqual((yield dut.dfi.phases[3].cke), 0b11)
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dut = SteererDUT(nranks=2, dfi_databits=16, nphases=4)
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run_simulation(dut, main_generator(dut))
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def test_odt_high_all_ranks(self):
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# odt should be 1 for all phases and ranks at all times
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# NOTE: only until dynamic odt is implemented
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def main_generator(dut):
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yield dut.steerer.sel[0].eq(STEER_CMD)
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yield dut.steerer.sel[1].eq(STEER_NOP)
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yield
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self.assertEqual((yield dut.dfi.phases[0].odt), 0b11)
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self.assertEqual((yield dut.dfi.phases[1].odt), 0b11)
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self.assertEqual((yield dut.dfi.phases[2].odt), 0b11)
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self.assertEqual((yield dut.dfi.phases[3].odt), 0b11)
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dut = SteererDUT(nranks=2, dfi_databits=16, nphases=4)
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run_simulation(dut, main_generator(dut))
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