127 lines
3.7 KiB
Python
Executable File
127 lines
3.7 KiB
Python
Executable File
# This file is Copyright (c) 2016-2018 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2016 Tim 'mithro' Ansell <mithro@mithis.com>
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# License: BSD
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import unittest
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import random
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from migen import *
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from litex.soc.interconnect.stream import *
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from litedram.common import *
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from litedram.frontend.bist import *
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from litedram.frontend.bist import _LiteDRAMBISTGenerator
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from litedram.frontend.bist import _LiteDRAMBISTChecker
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from test.common import *
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from litex.gen.sim import *
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class GenCheckDriver:
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def __init__(self, module):
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self.module = module
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def reset(self):
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yield self.module.reset.eq(1)
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yield
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yield self.module.reset.eq(0)
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yield
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def run(self, base, length):
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yield self.module.base.eq(base)
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yield self.module.length.eq(length)
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yield self.module.start.eq(1)
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yield
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yield self.module.start.eq(0)
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yield
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while((yield self.module.done) == 0):
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yield
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if hasattr(self.module, "errors"):
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self.errors = (yield self.module.errors)
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class TestBIST(unittest.TestCase):
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def test_generator(self):
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port = LiteDRAMNativeWritePort(address_width=32, data_width=32)
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def main_generator(dut):
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self.errors = 0
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# test incr
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yield dut.ce.eq(1)
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yield dut.random_enable.eq(0)
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yield
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for i in range(1024):
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data = (yield dut.o)
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if data != i:
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self.errors += 1
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yield
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# test random
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datas = []
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yield dut.ce.eq(1)
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yield dut.random_enable.eq(1)
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for i in range(1024):
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data = (yield dut.o)
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if data in datas:
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self.errors += 1
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datas.append(data)
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yield
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# dut
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dut = Generator(23, n_state=23, taps=[17, 22])
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# simulation
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generators = [main_generator(dut)]
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run_simulation(dut, main_generator(dut), vcd_name="generator.vcd")
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self.assertEqual(self.errors, 0)
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def test_bist(self):
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class DUT(Module):
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def __init__(self):
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self.write_port = LiteDRAMNativeWritePort(address_width=32, data_width=32)
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self.read_port = LiteDRAMNativeReadPort(address_width=32, data_width=32)
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self.submodules.generator = _LiteDRAMBISTGenerator(self.write_port)
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self.submodules.checker = _LiteDRAMBISTChecker(self.read_port)
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def main_generator(dut, mem):
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generator = GenCheckDriver(dut.generator)
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checker = GenCheckDriver(dut.checker)
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# write
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yield from generator.reset()
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yield from generator.run(16, 64)
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# read (no errors)
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yield from checker.reset()
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yield from checker.run(16, 64)
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assert checker.errors == 0
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# corrupt memory (using generator)
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yield from generator.reset()
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yield from generator.run(16 + 60, 64)
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# read (4 errors)
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yield from checker.reset()
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yield from checker.run(16, 64)
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assert checker.errors != 0
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# read (no errors)
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yield from checker.reset()
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yield from checker.run(16 + 60, 64)
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assert checker.errors == 0
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# dut
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dut = DUT()
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mem = DRAMMemory(32, 128)
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# simulation
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generators = [
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main_generator(dut, mem),
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mem.write_handler(dut.write_port),
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mem.read_handler(dut.read_port)
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]
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run_simulation(dut, generators, vcd_name="bist.vcd")
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