55 lines
1.6 KiB
Python
55 lines
1.6 KiB
Python
from litex.gen import *
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from litex.soc.interconnect.stream import *
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from litedram.common import LiteDRAMPort
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from litedram.frontend.bist import LiteDRAMBISTGenerator
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from litedram.frontend.bist import LiteDRAMBISTChecker
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from test.common import DRAMMemory
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class TB(Module):
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def __init__(self):
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self.write_port = LiteDRAMPort(aw=32, dw=32, cd="sys")
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self.read_port = LiteDRAMPort(aw=32, dw=32, cd="sys")
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self.submodules.generator = LiteDRAMBISTGenerator(self.write_port)
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self.submodules.checker = LiteDRAMBISTChecker(self.read_port)
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def main_generator(dut):
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for i in range(100):
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yield
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# write
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yield dut.generator.base.storage.eq(16)
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yield dut.generator.length.storage.eq(64)
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yield
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yield dut.generator.shoot.re.eq(1)
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yield
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yield dut.generator.shoot.re.eq(0)
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yield
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while((yield dut.generator.done.status) == 0):
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yield
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# read
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yield dut.checker.base.storage.eq(16)
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yield dut.checker.length.storage.eq(64)
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yield
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yield dut.checker.shoot.re.eq(1)
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yield
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yield dut.checker.shoot.re.eq(0)
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yield
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while((yield dut.checker.done.status) == 0):
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yield
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# check
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print("errors {:d}".format((yield dut.checker.error_count.status)))
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yield
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if __name__ == "__main__":
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tb = TB()
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mem = DRAMMemory(32, 128)
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generators = {
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"sys" : [main_generator(tb),
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mem.write_generator(tb.write_port),
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mem.read_generator(tb.read_port)]
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}
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clocks = {"sys": 10}
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run_simulation(tb, generators, clocks, vcd_name="sim.vcd")
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