145 lines
4.9 KiB
Python
145 lines
4.9 KiB
Python
#
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# This file is part of LiteDRAM.
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#
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# Bench Test ---------------------------------------------------------------------------------------
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def s7_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_timeout=5):
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import time
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from litex import RemoteClient
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wb = RemoteClient()
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wb.open()
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# # #
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class SoCCtrl:
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@staticmethod
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def reboot():
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wb.regs.ctrl_reset.write(1)
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@staticmethod
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def load_rom(filename):
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from litex.soc.integration.common import get_mem_data
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rom_data = get_mem_data(filename, "little")
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for i, data in enumerate(rom_data):
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wb.write(wb.mems.rom.base + 4*i, data)
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class ClkReg1:
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def __init__(self, value=0):
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self.unpack(value)
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def unpack(self, value):
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self.low_time = (value >> 0) & (2**6 - 1)
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self.high_time = (value >> 6) & (2**6 - 1)
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self.reserved = (value >> 12) & (2**1 - 1)
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self.phase_mux = (value >> 13) & (2**3 - 1)
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def pack(self):
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value = (self.low_time << 0)
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value |= (self.high_time << 6)
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value |= (self.reserved << 12)
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value |= (self.phase_mux << 13)
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return value
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def __repr__(self):
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s = "ClkReg1:\n"
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s += " low_time: {:d}\n".format(self.low_time)
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s += " high_time: {:d}\n".format(self.high_time)
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s += " reserved: {:d}\n".format(self.reserved)
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s += " phase_mux: {:d}".format(self.phase_mux)
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return s
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class ClkReg2:
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def __init__(self, value = 0):
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self.unpack(value)
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def unpack(self, value):
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self.delay_time = (value >> 0) & (2**6 - 1)
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self.no_count = (value >> 6) & (2**1 - 1)
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self.edge = (value >> 7) & (2**1 - 1)
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self.mx = (value >> 8) & (2**2 - 1)
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self.frac_wf_r = (value >> 10) & (2**1 - 1)
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self.frac_en = (value >> 11) & (2**1 - 1)
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self.frac = (value >> 12) & (2**3 - 1)
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self.reserved = (value >> 15) & (2**1 - 1)
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def pack(self):
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value = (self.delay_time << 0)
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value |= (self.no_count << 6)
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value |= (self.edge << 7)
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value |= (self.mx << 8)
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value |= (self.frac_wf_r << 10)
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value |= (self.frac_en << 11)
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value |= (self.frac << 12)
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value |= (self.reserved << 15)
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return value
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def __repr__(self):
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s = "ClkReg2:\n"
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s += " delay_time: {:d}\n".format(self.delay_time)
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s += " no_count: {:d}\n".format(self.no_count)
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s += " edge: {:d}\n".format(self.edge)
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s += " mx: {:d}\n".format(self.mx)
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s += " frac_wf_r: {:d}\n".format(self.frac_wf_r)
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s += " frac_en: {:d}\n".format(self.frac_en)
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s += " frac: {:d}\n".format(self.frac)
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s += " reserved: {:d}".format(self.reserved)
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return s
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class S7PLL:
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def reset(self):
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wb.regs.crg_main_pll_drp_reset.write(1)
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def read(self, adr):
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wb.regs.crg_main_pll_drp_adr.write(adr)
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wb.regs.crg_main_pll_drp_read.write(1)
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return wb.regs.crg_main_pll_drp_dat_r.read()
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def write(self, adr, value):
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wb.regs.crg_main_pll_drp_adr.write(adr)
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wb.regs.crg_main_pll_drp_dat_w.write(value)
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wb.regs.crg_main_pll_drp_write.write(1)
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# # #
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ctrl = SoCCtrl()
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ctrl.load_rom(bios_filename)
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ctrl.reboot()
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s7pll = S7PLL()
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clkout0_clkreg1 = ClkReg1(s7pll.read(0x08))
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tested_vco_divs = []
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for clk_freq in range(int(freq_min), int(freq_max), int(freq_step)):
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vco_div = int(vco_freq/clk_freq)
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if vco_div in tested_vco_divs:
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continue
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tested_vco_divs.append(vco_div)
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print("Reconfig Main PLL to {}MHz...".format(vco_freq/vco_div/1e6))
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clkout0_clkreg1.high_time = vco_div//2 + vco_div%2
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clkout0_clkreg1.low_time = vco_div//2
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s7pll.write(0x08, clkout0_clkreg1.pack())
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print("Measuring sys_clk...")
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duration = 5e-1
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start = wb.regs.crg_sys_clk_counter.read()
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time.sleep(duration)
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end = wb.regs.crg_sys_clk_counter.read()
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print("sys_clk: {:3.2f}MHz".format((end-start)/(1e6*duration)))
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print("Reboot SoC and get BIOS log...")
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ctrl.reboot()
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start = time.time()
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while (time.time() - start) < bios_timeout:
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if wb.regs.uart_xover_rxfull.read():
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for c in wb.read(wb.regs.uart_xover_rxtx.addr, 16, burst="fixed"):
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print("{:c}".format(c), end="")
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# # #
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wb.close()
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