47 lines
2.0 KiB
Python
47 lines
2.0 KiB
Python
#
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# This file is part of LiteDRAM.
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#
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# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import filecmp
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import unittest
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from litex.build.tools import write_to_file
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from litedram.init import get_sdram_phy_c_header, get_sdram_phy_py_header
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def compare_with_reference(content, filename):
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write_to_file(filename, content)
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r = filecmp.cmp(filename, os.path.join("test", "reference", filename))
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os.remove(filename)
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return r
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class TestInit(unittest.TestCase):
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def test_sdr(self):
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from litex_boards.targets.minispartan6 import BaseSoC
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soc = BaseSoC()
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c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
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py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
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self.assertEqual(compare_with_reference(c_header, "sdr_init.h"), True)
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self.assertEqual(compare_with_reference(py_header, "sdr_init.py"), True)
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def test_ddr3(self):
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from litex_boards.targets.kc705 import BaseSoC
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soc = BaseSoC()
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c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
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py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
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self.assertEqual(compare_with_reference(c_header, "ddr3_init.h"), True)
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self.assertEqual(compare_with_reference(py_header, "ddr3_init.py"), True)
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def test_ddr4(self):
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from litex_boards.targets.kcu105 import BaseSoC
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soc = BaseSoC(max_sdram_size=0x4000000)
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c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
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py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
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self.assertEqual(compare_with_reference(c_header, "ddr4_init.h"), True)
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self.assertEqual(compare_with_reference(py_header, "ddr4_init.py"), True)
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