100 lines
2.9 KiB
Python
100 lines
2.9 KiB
Python
from litex.gen import *
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def toggle_re(reg):
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resig = reg.re
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# Check that reset isn't set
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reval = yield resig
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assert not reval, reval
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yield resig.eq(1)
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yield
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yield resig.eq(0)
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def reset_bist_module(module):
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# Toggle the reset
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yield from toggle_re(module.reset)
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# Takes 8 more clock cycles for the reset to have an effect
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for i in range(8):
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yield
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# Check some initial conditions are correct after reset.
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running = yield module.core.running
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assert running == 0, running
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done = yield module.done.status
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assert not done, done
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def seed_to_data(seed, random=True, nbits=32):
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if nbits == 32:
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if random:
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return (seed * 0x31415979 + 1) & 0xffffffff
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else:
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return seed
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else:
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assert nbits%32 == 0
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data = 0
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for i in range(nbits//32):
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data = data << 32
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data |= seed_to_data(seed*nbits//32 + i, random, 32)
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return data
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class DRAMMemory:
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def __init__(self, width, depth, init=[]):
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self.width = width
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self.depth = depth
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self.mem = []
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for d in init:
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self.mem.append(d)
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for _ in range(depth-len(init)):
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self.mem.append(0)
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@passive
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def read_generator(self, dram_port):
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address = 0
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pending = 0
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yield dram_port.cmd.ready.eq(0)
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while True:
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yield dram_port.rdata.valid.eq(0)
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if pending:
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yield dram_port.rdata.valid.eq(1)
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yield dram_port.rdata.data.eq(self.mem[address%self.depth])
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yield
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yield dram_port.rdata.valid.eq(0)
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yield dram_port.rdata.data.eq(0)
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pending = 0
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elif (yield dram_port.cmd.valid):
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pending = not (yield dram_port.cmd.we)
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address = (yield dram_port.cmd.adr)
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if pending:
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yield dram_port.cmd.ready.eq(1)
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yield
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yield dram_port.cmd.ready.eq(0)
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yield
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@passive
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def write_generator(self, dram_port):
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address = 0
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pending = 0
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yield dram_port.cmd.ready.eq(0)
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while True:
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yield dram_port.wdata.ready.eq(0)
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if pending:
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yield dram_port.wdata.ready.eq(1)
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yield
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self.mem[address%self.depth] = (yield dram_port.wdata.data) # TODO manage we
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yield dram_port.wdata.ready.eq(0)
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yield
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pending = 0
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yield
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elif (yield dram_port.cmd.valid):
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pending = (yield dram_port.cmd.we)
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address = (yield dram_port.cmd.adr)
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if pending:
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yield dram_port.cmd.ready.eq(1)
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yield
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yield dram_port.cmd.ready.eq(0)
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yield
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