litedram/examples
Florent Kermarrec fe478382e1 litedram_gen: expose a Bus Slave port instead of a CSR port.
The logic overhead is minimal and it makes things easier with more flexibility:
- since the main Bus is arbitrated, CPU and Bus Slave can coexist.
- integration is easier in LiteX.
- bridging to APB/AXI is easier.
2020-05-11 22:47:09 +02:00
..
arty.yml litedram_gen: expose a Bus Slave port instead of a CSR port. 2020-05-11 22:47:09 +02:00
genesys2.yml litedram_gen: expose a Bus Slave port instead of a CSR port. 2020-05-11 22:47:09 +02:00
nexys4ddr.yml litedram_gen: expose a Bus Slave port instead of a CSR port. 2020-05-11 22:47:09 +02:00
versa_ecp5.yml litedram_gen: expose a Bus Slave port instead of a CSR port. 2020-05-11 22:47:09 +02:00