liteeth/examples/udp_s7phyrgmii.yml

# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD

# PHY ----------------------------------------------------------------------
phy:         LiteEthS7PHYRGMII
vendor:      xilinx
# Core ---------------------------------------------------------------------
clk_freq:    125e6
core:        udp
mac_address: 0x10e2d5000000
ip_address:  192.168.1.50
port:        6000
liteeth/gen: initial switch to YAML config file (similar to LiteDRAM/LitePCIe) 2020-02-11 18:18:22 -05:00			`# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>`
			`# License: BSD`

Move more options to config file 2020-02-12 09:09:57 -05:00			`# PHY ----------------------------------------------------------------------`
			`phy: LiteEthS7PHYRGMII`
			`vendor: xilinx`
			`# Core ---------------------------------------------------------------------`
examples: increase clk_freq to 125MHz on udp_s7phyrgmii.yml. 2020-03-19 17:01:33 -04:00			`clk_freq: 125e6`
Move more options to config file 2020-02-12 09:09:57 -05:00			`core: udp`
			`mac_address: 0x10e2d5000000`
			`ip_address: 192.168.1.50`
			`port: 6000`