95 lines
3.4 KiB
Python
95 lines
3.4 KiB
Python
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#!/usr/bin/env python3
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#
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# This file is part of LiteEth.
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#
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# Copyright (c) 2023 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen import *
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from litex_boards.platforms import xilinx_kc705
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from litex.soc.cores.clock import *
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from liteeth.phy.k7_1000basex import K7_1000BASEX
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.cd_sys = ClockDomain()
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self.cd_eth = ClockDomain()
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# # #
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# Main PLL.
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self.main_pll = main_pll = USMMCM(speedgrade=-2)
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self.comb += main_pll.reset.eq(platform.request("cpu_reset"))
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main_pll.register_clkin(platform.request("clk200"), 200e6)
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main_pll.create_clkout(self.cd_sys, sys_clk_freq)
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main_pll.create_clkout(self.cd_eth, 200e6)
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# Bench SoC ----------------------------------------------------------------------------------------
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class BenchSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(125e6)):
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platform = xilinx_kc705.Platform()
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# SoCMini ----------------------------------------------------------------------------------
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SoCMini.__init__(self, platform, clk_freq=sys_clk_freq,
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ident = "LiteEth bench on KC705",
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ident_version = True
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)
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# Etherbone --------------------------------------------------------------------------------
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self.ethphy = K7_1000BASEX(
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refclk_or_clk_pads = self.crg.cd_eth.clk,
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data_pads = self.platform.request("sfp", 0),
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sys_clk_freq = self.clk_freq,
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with_csr = False
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)
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self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
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self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]")
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self.add_etherbone(phy=self.ethphy, buffer_depth=255)
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# SRAM -------------------------------------------------------------------------------------
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self.add_ram("sram", 0x20000000, 0x1000)
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# Leds -------------------------------------------------------------------------------------
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from litex.soc.cores.led import LedChaser
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Main ---------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteEth Bench on KC705")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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args = parser.parse_args()
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soc = BenchSoC()
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builder = Builder(soc, csr_csv="csr.csv")
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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