liteeth/examples/wishbone_mii.yml

#
# This file is part of LiteEth.
#
# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause

# PHY ----------------------------------------------------------------------
phy:        LiteEthPHYMII
vendor:     xilinx
# Core ---------------------------------------------------------------------
clk_freq:   100e6
core:       wishbone
endianness: big

soc:
    mem_map:
        ethmac: 0x50000000
add SPDX License identifier to header and specify file is part or LiteEth. Artix7/Ultrascale 1000BaseX is reused from MiSoC/LiteEthMini, specify it. 2020-08-23 10:06:55 -04:00			`#`
			`# This file is part of LiteEth.`
			`#`
			`# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>`
			`# SPDX-License-Identifier: BSD-2-Clause`
liteeth/gen: initial switch to YAML config file (similar to LiteDRAM/LitePCIe) 2020-02-11 18:18:22 -05:00
Move more options to config file 2020-02-12 09:09:57 -05:00			`# PHY ----------------------------------------------------------------------`
			`phy: LiteEthPHYMII`
			`vendor: xilinx`
			`# Core ---------------------------------------------------------------------`
			`clk_freq: 100e6`
			`core: wishbone`
			`endianness: big`
Make memory/CSR regions customizable in config Also remove interrupt mapping, since it's unused without a CPU anyway. 2020-02-12 09:10:59 -05:00
Allow changing all SoC options through YAML config 2020-03-17 13:52:44 -04:00			`soc:`
			`mem_map:`
			`ethmac: 0x50000000`