120 lines
3.5 KiB
Python
120 lines
3.5 KiB
Python
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#!/usr/bin/env python3
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import argparse
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from litex.gen import *
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from litex.build.generic_platform import *
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from litex.build.xilinx.platform import XilinxPlatform
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from litex.soc.interconnect import wishbone
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from liteeth.phy.mii import LiteEthPHYMII
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from liteeth.core.mac import LiteEthMAC
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_io = [
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("sys_clock", 0, Pins(1)),
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("sys_reset", 1, Pins(1)),
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("wishbone", 0,
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Subsignal("adr", Pins(30)),
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Subsignal("dat_r", Pins(32)),
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Subsignal("dat_w", Pins(32)),
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Subsignal("sel", Pins(4)),
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Subsignal("cyc", Pins(1)),
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Subsignal("stb", Pins(1)),
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Subsignal("ack", Pins(1)),
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Subsignal("we", Pins(1)),
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Subsignal("cti", Pins(3)),
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Subsignal("bte", Pins(2)),
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Subsignal("err", Pins(1))
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),
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("eth_clocks", 0,
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Subsignal("tx", Pins(1)),
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Subsignal("rx", Pins(1)),
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),
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("eth", 0,
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Subsignal("rst_n", Pins(1)),
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Subsignal("mdio", Pins(1)),
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Subsignal("mdc", Pins(1)),
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Subsignal("dv", Pins(1)),
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Subsignal("rx_er", Pins(1)),
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Subsignal("rx_data", Pins(4)),
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Subsignal("tx_en", Pins(4)),
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Subsignal("tx_data", Pins(4)),
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Subsignal("col", Pins(1)),
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Subsignal("crs", Pins(1))
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)
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]
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class CorePlatform(XilinxPlatform):
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name = "core"
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7", _io)
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def do_finalize(self, *args, **kwargs):
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pass
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class WishboneBridge(Module):
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def __init__(self, interface):
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self.wishbone = interface
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class Core(SoCCore):
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csr_peripherals = (
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"ethphy",
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"ethmac"
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)
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csr_map = dict((n, v) for v, n in enumerate(csr_peripherals, start=16))
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csr_map.update(SoCCore.csr_map)
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interrupt_map = {
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"ethmac": 2,
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}
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interrupt_map.update(SoCCore.interrupt_map)
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mem_map = {
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"ethmac": 0x50000000
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}
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mem_map.update(SoCCore.mem_map)
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def __init__(self, clk_freq=100*1000000):
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platform = CorePlatform()
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SoCCore.__init__(self, platform,
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clk_freq=clk_freq,
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cpu_type=None,
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integrated_rom_size=0x0,
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integrated_sram_size=0x0,
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integrated_main_ram_size=0x0,
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csr_address_width=14, csr_data_width=8,
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with_uart=False, with_timer=False)
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self.submodules.crg = CRG(platform.request("sys_clock"),
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platform.request("sys_reset"))
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# ethernet
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self.submodules.ethphy = LiteEthPHYMII(platform.request("eth_clocks"),
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platform.request("eth"))
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
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self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
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self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
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# wishbone
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self.add_cpu_or_bridge(WishboneBridge(platform.request("wishbone")))
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self.add_wb_master(self.cpu_or_bridge.wishbone)
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def main():
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parser = argparse.ArgumentParser(description="LiteEth core builder")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = Core(**soc_core_argdict(args))
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builder = Builder(soc, output_dir="liteeth", compile_gateware=False, csr_csv="liteeth/csr.csv")
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builder.build(build_name="liteeth")
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if __name__ == "__main__":
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main()
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