2015-11-13 18:42:33 -05:00
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from litex.soc.interconnect.stream_sim import *
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2015-09-12 14:53:14 -04:00
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2015-11-13 18:42:33 -05:00
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from liteeth.common import *
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2015-09-07 07:28:02 -04:00
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def print_phy(s):
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print_with_prefix(s, "[PHY]")
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# PHY model
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2016-03-15 15:14:33 -04:00
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class PHYSource(PacketStreamer):
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2015-09-07 07:28:02 -04:00
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def __init__(self, dw):
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PacketStreamer.__init__(self, eth_phy_description(dw))
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class PHYSink(PacketLogger):
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def __init__(self, dw):
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PacketLogger.__init__(self, eth_phy_description(dw))
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class PHY(Module):
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def __init__(self, dw, debug=False):
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self.dw = dw
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self.debug = debug
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2016-03-15 15:14:33 -04:00
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self.submodules.phy_source = PHYSource(dw)
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2015-09-07 07:28:02 -04:00
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self.submodules.phy_sink = PHYSink(dw)
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self.source = self.phy_source.source
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self.sink = self.phy_sink.sink
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self.mac_callback = None
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def set_mac_callback(self, callback):
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self.mac_callback = callback
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def send(self, datas):
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packet = Packet(datas)
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if self.debug:
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r = ">>>>>>>>\n"
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r += "length " + str(len(datas)) + "\n"
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for d in datas:
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r += "{:02x}".format(d)
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print_phy(r)
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self.phy_source.send(packet)
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def receive(self):
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yield from self.phy_sink.receive()
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if self.debug:
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r = "<<<<<<<<\n"
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r += "length " + str(len(self.phy_sink.packet)) + "\n"
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for d in self.phy_sink.packet:
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r += "{:02x}".format(d)
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print_phy(r)
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self.packet = self.phy_sink.packet
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2016-03-21 14:30:47 -04:00
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def generator(self):
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2015-09-07 07:28:02 -04:00
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while True:
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yield from self.receive()
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if self.mac_callback is not None:
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self.mac_callback(self.packet)
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