mac/crc/LiteEthMACCRC32: Rename last_be to be and add comments.
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@ -86,41 +86,44 @@ class LiteEthMACCRC32(LiteXModule):
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----------
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data : in
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Data input.
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last_be : in
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Valid byte in data input (optional).
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be : in
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Data byte enable (optional, defaults to full word).
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value : out
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CRC value (used for generator).
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error : out
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CRC error (used for checker).
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"""
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width = 32
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polynom = 0x04C11DB7
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polynom = 0x04c11db7
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init = 2**width-1
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check = 0xC704DD7B
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check = 0xc704dd7b
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def __init__(self, data_width):
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self.data = Signal(data_width)
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self.last_be = Signal(data_width//8, reset=2**(data_width//8 - 1))
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self.be = Signal(data_width//8, reset=2**data_width//8 - 1)
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self.value = Signal(self.width)
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self.error = Signal()
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# # #
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# Since the data can end at any byte end, indicated by `last_be`
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# maintain separate engines for each 8 byte increment in the data word
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# Create a CRC Engine for each byte segment.
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# Ex for a 32-bit Data-Path, we create 4 engines: 8, 16, 24 and 32-bit engines.
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engines = []
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for e in range(data_width//8):
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engines.append(LiteEthMACCRCEngine((e+1)*8, self.width, self.polynom))
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for n in range(data_width//8):
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engines.append(LiteEthMACCRCEngine((n + 1)*8, self.width, self.polynom))
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self.submodules += engines
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# Register Full-Word CRC Engine (last one).
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reg = Signal(self.width, reset=self.init)
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self.sync += reg.eq(engines[-1].crc_next)
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for e in range(data_width//8):
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# Select CRC Engine/Result.
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for n in range(data_width//8):
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self.comb += [
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engines[e].data.eq(self.data[:(e+1)*8]),
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engines[e].crc_prev.eq(reg),
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If(self.last_be[e],
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self.value.eq(reverse_bits(~engines[e].crc_next)),
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self.error.eq(engines[e].crc_next != self.check),
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engines[n].data.eq(self.data[:(n + 1)*8]),
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engines[n].crc_prev.eq(reg),
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If(self.be[n],
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self.value.eq(reverse_bits(~engines[n].crc_next)),
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self.error.eq(engines[n].crc_next != self.check),
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)
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]
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@ -170,7 +173,7 @@ class LiteEthMACCRCInserter(LiteXModule):
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fsm.act("COPY",
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crc.ce.eq(sink.valid & source.ready),
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crc.data.eq(sink.data),
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crc.last_be.eq(sink.last_be),
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crc.be.eq(sink.last_be),
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sink.connect(source),
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source.last.eq(0),
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source.last_be.eq(0),
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@ -302,7 +305,7 @@ class LiteEthMACCRCChecker(LiteXModule):
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)
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self.comb += [
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crc.data.eq(sink.data),
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crc.last_be.eq(sink.last_be),
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crc.be.eq(sink.last_be),
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]
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fsm.act("IDLE",
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If(sink.valid & sink.ready,
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