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mac/crc: Add 64 bit support to checker
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parent
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commit
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1 changed files with 45 additions and 16 deletions
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@ -10,6 +10,7 @@
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from functools import reduce
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from operator import xor
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from collections import OrderedDict
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from math import ceil
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from liteeth.common import *
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@ -293,10 +294,10 @@ class LiteEthMACCRCChecker(Module):
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# # #
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dw = len(sink.data)
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assert dw in [8, 32]
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assert dw in [8, 32, 64]
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crc = crc_class(dw)
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self.submodules += crc
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ratio = crc.width//dw
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ratio = ceil(crc.width/dw)
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fifo = ResetInserter()(stream.SyncFIFO(description, ratio + 1))
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self.submodules += fifo
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@ -316,19 +317,6 @@ class LiteEthMACCRCChecker(Module):
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sink.connect(fifo.sink),
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fifo.sink.valid.eq(fifo_in),
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self.sink.ready.eq(fifo_in),
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source.valid.eq(sink.valid & fifo_full),
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source.last.eq(sink.last),
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fifo.source.ready.eq(fifo_out),
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source.payload.eq(fifo.source.payload),
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source.last_be.eq(sink.last_be),
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# `source.error` has a width > 1 for dw > 8, but since the crc error
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# applies to the whole ethernet packet, all the bytes are marked as
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# containing an error. This way later reducing the data width
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# doesn't run into issues with missing the error
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source.error.eq(sink.error | Replicate(crc.error, dw//8)),
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self.error.eq(source.valid & source.last & crc.error),
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]
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fsm.act("RESET",
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@ -346,15 +334,56 @@ class LiteEthMACCRCChecker(Module):
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NextState("COPY")
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)
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)
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last_be = Signal().like(sink.last_be)
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crc_error = Signal()
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fsm.act("COPY",
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fifo.source.ready.eq(fifo_out),
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source.valid.eq(sink.valid & fifo_full),
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source.payload.eq(fifo.source.payload),
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If(dw <= 32,
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source.last.eq(sink.last),
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source.last_be.eq(sink.last_be),
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# For dw == 64 bit, we need to look wether the last word contains only the crc value or both crc and data
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# In the latter case, the last word also needs to be output
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# In both cases, last_be needs to be adjusted for the new end position
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).Elif(sink.last_be & 0xF,
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source.last.eq(sink.last),
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source.last_be.eq(sink.last_be << (dw//8 - 4)),
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).Else(
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NextValue(last_be, sink.last_be >> 4),
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NextValue(crc_error, crc.error),
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),
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# `source.error` has a width > 1 for dw > 8, but since the crc error
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# applies to the whole ethernet packet, all the bytes are marked as
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# containing an error. This way later reducing the data width
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# doesn't run into issues with missing the error
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source.error.eq(sink.error | Replicate(crc.error, dw//8)),
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self.error.eq(sink.valid & sink.last & crc.error),
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If(sink.valid & sink.ready,
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crc.ce.eq(1),
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If(sink.last,
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# Can only happen for dw == 64
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If(sink.last & (sink.last_be > 0xF),
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NextState("COPY_LAST"),
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).Elif(sink.last,
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NextState("RESET")
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)
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)
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)
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# If the last sink word contains both data and the crc value, shift out
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# the last value here. Can only happen for dw == 64
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fsm.act("COPY_LAST",
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fifo.source.connect(source),
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source.error.eq(fifo.source.error | Replicate(crc_error, dw//8)),
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source.last_be.eq(last_be),
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If(source.valid & source.ready,
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NextState("RESET")
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)
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)
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class LiteEthMACCRC32Checker(LiteEthMACCRCChecker):
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def __init__(self, description):
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