mac/crc: Implement 32 bit support in checker
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@ -242,9 +242,9 @@ class LiteEthMACCRCChecker(Module):
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Attributes
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----------
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sink : in
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Packet octets with CRC.
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Packet data with CRC.
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source : out
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Packet octets without CRC and "error" set to 0
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Packet data without CRC and "error" set to 0
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on last when CRC OK / set to 1 when CRC KO.
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error : out
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Pulses every time a CRC error is detected.
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@ -258,6 +258,7 @@ class LiteEthMACCRCChecker(Module):
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# # #
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dw = len(sink.data)
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assert dw in [8, 32]
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crc = crc_class(dw)
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self.submodules += crc
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ratio = crc.width//dw
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@ -285,8 +286,13 @@ class LiteEthMACCRCChecker(Module):
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source.last.eq(sink.last),
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fifo.source.ready.eq(fifo_out),
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source.payload.eq(fifo.source.payload),
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source.last_be.eq(sink.last_be),
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source.error.eq(sink.error | crc.error),
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# `source.error` has a width > 1 for dw > 8, but since the crc error
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# applies to the whole ethernet packet, all the bytes are marked as
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# containing an error. This way later reducing the data width
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# doesn't run into issues with missing the error
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source.error.eq(sink.error | Replicate(crc.error, dw//8)),
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self.error.eq(source.valid & source.last & crc.error),
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]
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@ -295,7 +301,10 @@ class LiteEthMACCRCChecker(Module):
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fifo.reset.eq(1),
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NextState("IDLE"),
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)
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self.comb += crc.data.eq(sink.data)
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self.comb += [
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crc.data.eq(sink.data),
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crc.last_be.eq(sink.last_be),
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]
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fsm.act("IDLE",
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If(sink.valid & sink.ready,
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crc.ce.eq(1),
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