frontend/etherbone: simplify LiteEthEtherboneRecordReceiver.
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d96fdfc5e5
commit
06242564f7
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@ -215,20 +215,12 @@ class LiteEthEtherboneRecordReceiver(Module):
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base_addr_update = Signal()
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self.sync += If(base_addr_update, base_addr.eq(fifo.source.data))
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counter = Signal(max=512, reset_less=True)
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counter_reset = Signal()
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counter_ce = Signal()
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self.sync += \
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If(counter_reset,
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counter.eq(0)
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).Elif(counter_ce,
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counter.eq(counter + 1)
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)
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count = Signal(max=512, reset_less=True)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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fifo.source.ready.eq(1),
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counter_reset.eq(1),
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NextValue(count, 0),
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If(fifo.source.valid,
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base_addr_update.eq(1),
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If(fifo.source.wcount,
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@ -240,15 +232,15 @@ class LiteEthEtherboneRecordReceiver(Module):
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)
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fsm.act("RECEIVE_WRITES",
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source.valid.eq(fifo.source.valid),
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source.last.eq(counter == fifo.source.wcount-1),
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source.last.eq(count == fifo.source.wcount-1),
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source.count.eq(fifo.source.wcount),
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source.be.eq(fifo.source.byte_enable),
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source.addr.eq(base_addr[2:] + counter),
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source.addr.eq(base_addr[2:] + count),
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source.we.eq(1),
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source.data.eq(fifo.source.data),
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fifo.source.ready.eq(source.ready),
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If(source.valid & source.ready,
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counter_ce.eq(1),
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NextValue(count, count + 1),
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If(source.last,
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If(fifo.source.rcount,
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NextState("RECEIVE_BASE_RET_ADDR")
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@ -259,7 +251,7 @@ class LiteEthEtherboneRecordReceiver(Module):
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)
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)
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fsm.act("RECEIVE_BASE_RET_ADDR",
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counter_reset.eq(1),
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NextValue(count, 0),
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If(fifo.source.valid,
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base_addr_update.eq(1),
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NextState("RECEIVE_READS")
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@ -267,13 +259,13 @@ class LiteEthEtherboneRecordReceiver(Module):
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)
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fsm.act("RECEIVE_READS",
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source.valid.eq(fifo.source.valid),
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source.last.eq(counter == fifo.source.rcount-1),
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source.last.eq(count == fifo.source.rcount-1),
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source.count.eq(fifo.source.rcount),
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source.base_addr.eq(base_addr),
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source.addr.eq(fifo.source.data[2:]),
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fifo.source.ready.eq(source.ready),
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If(source.valid & source.ready,
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counter_ce.eq(1),
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NextValue(count, count + 1),
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If(source.last,
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NextState("IDLE")
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)
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