Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

liteeth/phy/1000basex: Avoid splitting transceiver instance since no longer useful with current Python version.

This commit is contained in:
Florent Kermarrec 2024-12-12 14:17:23 +01:00
parent 99d4073c6a
commit 0685079333
5 changed files with 765 additions and 787 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
liteeth/phy/k7_1000basex.py
View File

@ -341,9 +341,8 @@ class K7_1000BASEX(LiteXModule):
p_RX_DFE_XYD_CFG = 0b0000000000000,
# TX Configurable Driver Attributes
p_TX_PREDRIVER_MODE = 0b0
)
gtx_params.update(
p_TX_PREDRIVER_MODE = 0b0,
# CPLL Ports
o_CPLLFBCLKLOST = Open(),
o_CPLLLOCK = pll.lock,

9
liteeth/phy/ku_1000basex.py
View File

@ -200,8 +200,6 @@ class KU_1000BASEX(LiteXModule):
p_PROCESS_PAR = 0b010,
p_RATE_SW_USE_DRP = 0b1,
p_RESET_POWERSAVE_DISABLE = 0b0,
)
gth_params.update(
p_RXBUFRESET_TIME = 0b00011,
p_RXBUF_ADDR_MODE = "FAST",
p_RXBUF_EIDLE_HI_CNT = 0b1000,
@ -370,8 +368,6 @@ class KU_1000BASEX(LiteXModule):
p_RX_TUNE_AFE_OS = 0b10,
p_RX_WIDEMODE_CDR = 0b0,
p_RX_XCLK_SEL = "RXDES",
)
gth_params.update(
p_SAS_MAX_COM = 64,
p_SAS_MIN_COM = 36,
p_SATA_BURST_SEQ_LEN = 0b1110,
@ -469,8 +465,7 @@ class KU_1000BASEX(LiteXModule):
p_TX_XCLK_SEL = "TXOUT",
p_USE_PCS_CLK_PHASE_SEL = 0b0,
p_WB_MODE = 0b00,
)
gth_params.update(
i_CFGRESET = 0b0,
i_CLKRSVD0 = 0b0,
i_CLKRSVD1 = 0b0,
@ -703,8 +698,6 @@ class KU_1000BASEX(LiteXModule):
i_TXUSERRDY = 0b1,
i_TXUSRCLK2 = ClockSignal("eth_tx_half"),
i_TXUSRCLK = ClockSignal("eth_tx_half"),
)
gth_params.update(
o_BUFGTCE = Open(),
o_BUFGTCEMASK = Open(),
o_BUFGTDIV = Open(),

7
liteeth/phy/usp_gth_1000basex.py
View File

@ -229,8 +229,6 @@ class USP_GTH_1000BASEX(LiteXModule):
p_PROCESS_PAR = 0b010,
p_RATE_SW_USE_DRP = 0b1,
p_RESET_POWERSAVE_DISABLE = 0b0,
)
gth_params.update(
p_RXBUFRESET_TIME = 0b00011,
p_RXBUF_ADDR_MODE = "FULL",
p_RXBUF_EIDLE_HI_CNT = 0b1000,
@ -560,8 +558,7 @@ class USP_GTH_1000BASEX(LiteXModule):
p_USB_U2_SAS_MIN_COM = 36,
p_USE_PCS_CLK_PHASE_SEL = 0b0,
p_Y_ALL_MODE = 0b0,
)
gth_params.update(
i_CFGRESET = 0b0,
i_CLKRSVD0 = 0b0,
i_CLKRSVD1 = 0b0,
@ -766,8 +763,6 @@ class USP_GTH_1000BASEX(LiteXModule):
i_TXUSERRDY = 0b1,
i_TXUSRCLK2 = ClockSignal("eth_tx_half"),
i_TXUSRCLK = ClockSignal("eth_tx_half"),
)
gth_params.update(
o_BUFGTCE = Open(),
o_BUFGTCEMASK = Open(),
o_BUFGTDIV = Open(),

9
liteeth/phy/usp_gty_1000basex.py
View File

@ -233,8 +233,6 @@ class USP_GTY_1000BASEX(LiteXModule):
p_PCIE_RXPMA_CFG = 0b0010100000001010,
p_PCIE_TXPCS_CFG_GEN3 = 0b0010110010100100,
p_PCIE_TXPMA_CFG = 0b0010100000001010,
)
gty_params.update(
p_PCS_PCIE_EN = "FALSE",
p_PCS_RSVD0 = 0b0000000000000000,
p_PD_TRANS_TIME_FROM_P2 = 0b000000111100,
@ -342,8 +340,6 @@ class USP_GTY_1000BASEX(LiteXModule):
p_RXDFE_UT_CFG2 = 0b0000000000000000,
p_RXDFE_VP_CFG0 = 0b0000000000000000,
p_RXDFE_VP_CFG1 = 0b0000000000110011,
)
gty_params.update(
p_RXDLY_CFG = 0b0000000000010000,
p_RXDLY_LCFG = 0b0000000000110000,
p_RXELECIDLE_CFG = "SIGCFG_4",
@ -574,8 +570,7 @@ class USP_GTY_1000BASEX(LiteXModule):
p_USB_U2_SAS_MAX_COM = 64,
p_USB_U2_SAS_MIN_COM = 36,
p_USE_PCS_CLK_PHASE_SEL = 0b0,
)
gty_params.update(
i_CDRSTEPDIR = 0b0,
i_CDRSTEPSQ = 0b0,
i_CDRSTEPSX = 0b0,
@ -808,8 +803,6 @@ class USP_GTY_1000BASEX(LiteXModule):
i_TXUSERRDY = 0b1,
i_TXUSRCLK2 = ClockSignal("eth_tx_half"),
i_TXUSRCLK = ClockSignal("eth_tx_half"),
)
gty_params.update(
o_BUFGTCE = Open(),
o_BUFGTCEMASK = Open(),
o_BUFGTDIV = Open(),

2
liteeth/phy/v7_1000basex.py
View File

@ -343,8 +343,6 @@ class V7_1000BASEX(LiteXModule):
# TX Configurable Driver Attributes
p_TX_QPI_STATUS_EN = 0b0,
)
gth_params.update(
# CPLL Ports
o_CPLLFBCLKLOST = Open(),
o_CPLLLOCK = pll.lock,