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Merge branch 'generator-lattice' of git://github.com/ximinity/liteeth into ximinity-generator-lattice

This commit is contained in:
Florent Kermarrec 2020-02-11 23:34:52 +01:00
parent fcf7b245cb ae10eea860
commit 0954fa32b1
1 changed files with 36 additions and 15 deletions
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49
liteeth/gen.py Normal file → Executable file
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@ -26,6 +26,7 @@ from migen import *
from litex.build.generic_platform import * from litex.build.generic_platform import *
from litex.build.xilinx.platform import XilinxPlatform from litex.build.xilinx.platform import XilinxPlatform
from litex.build.lattice.platform import LatticePlatform
from litex.soc.interconnect import wishbone from litex.soc.interconnect import wishbone
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
@ -36,7 +37,9 @@ from liteeth.common import *
from liteeth.phy.mii import LiteEthPHYMII from liteeth.phy.mii import LiteEthPHYMII
from liteeth.phy.rmii import LiteEthPHYRMII from liteeth.phy.rmii import LiteEthPHYRMII
from liteeth.phy.gmii import LiteEthPHYGMII from liteeth.phy.gmii import LiteEthPHYGMII
from liteeth.phy.s7rgmii import LiteEthPHYRGMII
from liteeth.phy.s7rgmii import LiteEthPHYRGMII as s7phyrgmii
from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII as ecp5phyrgmii
from liteeth.mac import LiteEthMAC from liteeth.mac import LiteEthMAC
from liteeth.core import LiteEthUDPIPCore from liteeth.core import LiteEthUDPIPCore
@ -165,16 +168,20 @@ _io = [
# Platform ----------------------------------------------------------------------------------------- # Platform -----------------------------------------------------------------------------------------
class CorePlatform(XilinxPlatform): class LatticeCorePlatform(LatticePlatform):
name = "core" name = "core"
def __init__(self): def __init__(self, chip):
XilinxPlatform.__init__(self, "xc7", _io) LatticePlatform.__init__(self, chip, _io)
class XilinxCorePlatform(XilinxPlatform):
name = "core"
def __init__(self, chip):
XilinxPlatform.__init__(self, chip, _io)
# PHY Core ----------------------------------------------------------------------------------------- # PHY Core -----------------------------------------------------------------------------------------
class PHYCore(SoCMini): class PHYCore(SoCMini):
def __init__(self, phy, clk_freq): def __init__(self, phy, clk_freq, platform):
platform = CorePlatform()
SoCMini.__init__(self, platform, clk_freq=clk_freq) SoCMini.__init__(self, platform, clk_freq=clk_freq)
self.submodules.crg = CRG(platform.request("sys_clock"), self.submodules.crg = CRG(platform.request("sys_clock"),
platform.request("sys_reset")) platform.request("sys_reset"))
@ -189,7 +196,11 @@ class PHYCore(SoCMini):
ethphy = LiteEthPHYGMII(platform.request("gmii_eth_clocks"), ethphy = LiteEthPHYGMII(platform.request("gmii_eth_clocks"),
platform.request("gmii_eth")) platform.request("gmii_eth"))
elif phy == "rgmii": elif phy == "rgmii":
ethphy = LiteEthPHYRGMII(platform.request("rgmii_eth_clocks"), if type(platform) == LatticeCorePlatform:
ethphy = ecp5phyrgmii(platform.request("rgmii_eth_clocks"),
platform.request("rgmii_eth"))
elif type(platform) == XilinxCorePlatform:
ethphy = s7phyrgmii(platform.request("rgmii_eth_clocks"),
platform.request("rgmii_eth")) platform.request("rgmii_eth"))
else: else:
raise ValueError("Unsupported " + phy + " PHY"); raise ValueError("Unsupported " + phy + " PHY");
@ -209,8 +220,8 @@ class MACCore(PHYCore):
"ethmac": 0x50000000 "ethmac": 0x50000000
}) })
def __init__(self, phy, clk_freq, endianness): def __init__(self, phy, clk_freq, platform, endianness):
PHYCore.__init__(self, phy, clk_freq) PHYCore.__init__(self, phy, clk_freq, platform)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=endianness) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus)
@ -231,8 +242,8 @@ class MACCore(PHYCore):
# UDP Core ----------------------------------------------------------------------------------------- # UDP Core -----------------------------------------------------------------------------------------
class UDPCore(PHYCore): class UDPCore(PHYCore):
def __init__(self, phy, clk_freq, mac_address, ip_address, port): def __init__(self, phy, clk_freq, mac_address, ip_address, port, platform):
PHYCore.__init__(self, phy, clk_freq) PHYCore.__init__(self, phy, clk_freq, platform)
self.submodules.core = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), clk_freq) self.submodules.core = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), clk_freq)
udp_port = self.core.udp.crossbar.get_port(port, 8) udp_port = self.core.udp.crossbar.get_port(port, 8)
@ -284,17 +295,27 @@ def main():
parser.add_argument("--endianness", default="big", choices=("big", "little"), help="Wishbone endianness") parser.add_argument("--endianness", default="big", choices=("big", "little"), help="Wishbone endianness")
parser.add_argument("--mac_address", default=0x10e2d5000000, help="MAC address") parser.add_argument("--mac_address", default=0x10e2d5000000, help="MAC address")
parser.add_argument("--ip_address", default="192.168.1.50", help="IP address") parser.add_argument("--ip_address", default="192.168.1.50", help="IP address")
parser.add_argument("--platform", default="xilinx", help="Development board(lattice/xilinx)")
parser.add_argument("--chip", default="xc7", help="FPGA chip model e.g. xc7 or LFE5UM5G-45F-8BG381C")
args = parser.parse_args() args = parser.parse_args()
if args.platform == "lattice":
platform = LatticeCorePlatform(args.chip)
elif args.platform == "xilinx":
platform = XilinxCorePlatform(args.chip)
else:
raise ValueError("Unknown platform: {}".format(args.platform))
if args.core == "wishbone": if args.core == "wishbone":
soc = MACCore(phy=args.phy, clk_freq=int(100e6), endianness=args.endianness) soc = MACCore(phy=args.phy, clk_freq=int(100e6), platform=platform, endianness=args.endianness)
elif args.core == "udp": elif args.core == "udp":
soc = UDPCore(phy=args.phy, clk_freq=int(100e6), soc = UDPCore(phy=args.phy, clk_freq=int(100e6),
mac_address = args.mac_address, mac_address = args.mac_address,
ip_address = args.ip_address, ip_address = args.ip_address,
port = 6000) port = 6000,
platform = platform)
else: else:
raise ValueError raise ValueError("Unknown core: {}".format(args.core))
builder = Builder(soc, output_dir=args.output_dir, compile_gateware=False, csr_csv=os.path.join(args.output_dir, "csr.csv")) builder = Builder(soc, output_dir=args.output_dir, compile_gateware=False, csr_csv=os.path.join(args.output_dir, "csr.csv"))
builder.build(build_name="liteeth_core") builder.build(build_name="liteeth_core")