mac/__init__.py: Switch to LiteXModule and cosmetic improvements.
This commit is contained in:
Florent Kermarrec
parent
55bae6b7b4
commit
0bb6c53795
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@ -5,6 +5,8 @@
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# Copyright (c) 2023 LumiGuide Fietsdetectie B.V. <goemansrowan@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.gen import *
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from liteeth.common import *
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from liteeth.mac.common import *
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from liteeth.mac.core import LiteEthMACCore
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@ -12,7 +14,7 @@ from liteeth.mac.wishbone import LiteEthMACWishboneInterface
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# MAC ----------------------------------------------------------------------------------------------
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class LiteEthMAC(Module, AutoCSR):
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class LiteEthMAC(LiteXModule):
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def __init__(self, phy, dw,
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interface = "crossbar",
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endianness = "big",
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@ -34,7 +36,7 @@ class LiteEthMAC(Module, AutoCSR):
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assert interface in ["crossbar", "wishbone", "hybrid"]
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assert endianness in ["big", "little"]
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self.submodules.core = LiteEthMACCore(
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self.core = LiteEthMACCore(
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phy = phy,
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dw = dw,
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with_sys_datapath = with_sys_datapath,
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@ -46,9 +48,9 @@ class LiteEthMAC(Module, AutoCSR):
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)
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self.csrs = []
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if interface == "crossbar":
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self.submodules.crossbar = LiteEthMACCrossbar(dw)
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self.submodules.packetizer = LiteEthMACPacketizer(dw)
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self.submodules.depacketizer = LiteEthMACDepacketizer(dw)
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self.crossbar = LiteEthMACCrossbar(dw)
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self.packetizer = LiteEthMACPacketizer(dw)
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self.depacketizer = LiteEthMACDepacketizer(dw)
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self.comb += [
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self.crossbar.master.source.connect(self.packetizer.sink),
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self.packetizer.source.connect(self.core.sink),
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@ -76,13 +78,13 @@ class LiteEthMAC(Module, AutoCSR):
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# increases memory usage by a lot.
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if full_memory_we:
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wishbone_interface = FullMemoryWE()(wishbone_interface)
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self.submodules.interface = wishbone_interface
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self.interface = wishbone_interface
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self.ev, self.bus_rx, self.bus_tx = self.interface.sram.ev, self.interface.bus_rx, self.interface.bus_tx
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self.csrs = self.interface.get_csrs() + self.core.get_csrs()
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if interface == "hybrid":
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# Hardware MAC
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self.submodules.crossbar = LiteEthMACCrossbar(dw)
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self.submodules.mac_crossbar = LiteEthMACCoreCrossbar(self.core, self.crossbar, self.interface, dw, hw_mac)
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self.crossbar = LiteEthMACCrossbar(dw)
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self.mac_crossbar = LiteEthMACCoreCrossbar(self.core, self.crossbar, self.interface, dw, hw_mac)
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else:
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self.comb += self.interface.source.connect(self.core.sink)
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self.comb += self.core.source.connect(self.interface.sink)
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@ -97,20 +99,23 @@ class LiteEthMACCoreCrossbar(Module):
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rx_ready = Signal()
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rx_valid = Signal()
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# IP core packet processing
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self.submodules.packetizer = LiteEthMACPacketizer(dw)
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self.submodules.depacketizer = LiteEthMACDepacketizer(dw)
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# IP core packet processing.
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self.packetizer = LiteEthMACPacketizer(dw)
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self.depacketizer = LiteEthMACDepacketizer(dw)
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# HW Input Path.
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self.comb += [
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# HW input path
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# depacketizer -> crossbar
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# Depacketizer -> Crossbar.
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self.depacketizer.source.connect(crossbar.master.sink),
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# HW output path
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# crossbar -> packetizer -> tx_fifo
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]
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# HW Output Path.
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self.comb += [
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# Crossbar -> Packetizer.
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crossbar.master.source.connect(self.packetizer.sink),
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]
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# MAC filtering
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# MAC filtering.
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if hw_mac is not None:
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depacketizer = LiteEthMACDepacketizer(dw)
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hw_packetizer = LiteEthMACPacketizer(dw)
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@ -121,15 +126,23 @@ class LiteEthMACCoreCrossbar(Module):
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self.submodules += depacketizer, cpu_packetizer, hw_packetizer, hw_fifo, cpu_fifo
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# Core -> Depacketizer.
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self.comb += core.source.connect(depacketizer.sink)
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# HW FIFO -> HW Packetizer -> Depacketizer.
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self.comb += [
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core.source.connect(depacketizer.sink),
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hw_fifo.source.connect(hw_packetizer.sink),
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hw_packetizer.source.connect(self.depacketizer.sink),
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hw_packetizer.source.connect(depacketizer.sink),
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]
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# CPU FIFO -> CPU Packetizer -> Interface.
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self.comb += [
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cpu_fifo.source.connect(cpu_packetizer.sink),
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cpu_packetizer.source.connect(interface.sink),
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]
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# RX packetizer broadcast
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# RX packetizer broadcast.
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mac_local = Signal()
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mac_bcast = Signal()
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mac_mcast4 = Signal()
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@ -150,7 +163,7 @@ class LiteEthMACCoreCrossbar(Module):
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cpu_fifo.sink.valid.eq(rx_valid & ~mac_local),
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]
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else:
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# RX broadcast
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# RX broadcast.
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self.comb += [
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rx_ready.eq(interface.sink.ready & self.depacketizer.sink.ready),
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rx_valid.eq(rx_ready & core.source.valid),
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@ -161,8 +174,8 @@ class LiteEthMACCoreCrossbar(Module):
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self.depacketizer.sink.valid.eq(rx_valid),
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]
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# TX arbiter
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self.submodules.tx_arbiter_fsm = fsm = FSM(reset_state="IDLE")
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# TX arbiter.
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self.tx_arbiter_fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(interface.source.valid,
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NextState("WISHBONE")
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