liteeth/core: handle last_be.

This commit is contained in:
Florent Kermarrec 2021-02-10 19:18:55 +01:00
parent 497d4d6501
commit 0c003c8ee7
4 changed files with 13 additions and 5 deletions

View File

@ -36,7 +36,9 @@ class LiteEthARPTX(Module):
# # #
counter = Signal(max=max(arp_header.length, eth_min_len), reset_less=True)
packet_length = max(arp_header.length, eth_min_len)
packet_words = packet_length//(dw//8)
counter = Signal(max=packet_words, reset_less=True)
self.submodules.packetizer = packetizer = LiteEthARPPacketizer(dw)
@ -50,7 +52,8 @@ class LiteEthARPTX(Module):
)
)
self.comb += [
packetizer.sink.last.eq(counter == max(arp_header.length, eth_min_len)-1),
packetizer.sink.last.eq(counter == (packet_words - 1)),
packetizer.sink.last_be.eq(1 if len(packetizer.sink.last_be) == 1 else 2**(packet_length%(dw//8)-1)),
packetizer.sink.hwtype.eq(arp_hwtype_ethernet),
packetizer.sink.proto.eq(arp_proto_ip),
packetizer.sink.hwsize.eq(6),

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@ -34,7 +34,8 @@ class LiteEthICMPTX(Module):
packetizer.sink.code.eq(sink.code),
packetizer.sink.checksum.eq(sink.checksum),
packetizer.sink.quench.eq(sink.quench),
packetizer.sink.data.eq(sink.data)
packetizer.sink.data.eq(sink.data),
packetizer.sink.last_be.eq(sink.last_be)
]
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
@ -104,7 +105,8 @@ class LiteEthICMPRX(Module):
source.ip_address.eq(sink.ip_address),
source.length.eq(sink.length - icmp_header.length),
source.data.eq(depacketizer.source.data),
source.error.eq(depacketizer.source.error)
source.error.eq(depacketizer.source.error),
source.last_be.eq(depacketizer.source.last_be)
]
fsm.act("PRESENT",
source.valid.eq(depacketizer.source.valid),

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@ -106,6 +106,7 @@ class LiteEthIPTX(Module):
self.comb += [
packetizer.sink.valid.eq(sink.valid & checksum.done),
packetizer.sink.last.eq(sink.last),
packetizer.sink.last_be.eq(sink.last_be),
sink.ready.eq(packetizer.sink.ready & checksum.done),
packetizer.sink.target_ip.eq(sink.ip_address),
packetizer.sink.protocol.eq(sink.protocol),
@ -231,7 +232,8 @@ class LiteEthIPRX(Module):
source.protocol.eq(depacketizer.source.protocol),
source.ip_address.eq(depacketizer.source.sender_ip),
source.data.eq(depacketizer.source.data),
source.error.eq(depacketizer.source.error)
source.error.eq(depacketizer.source.error),
source.last_be.eq(depacketizer.source.last_be)
]
fsm.act("PRESENT",
source.valid.eq(depacketizer.source.valid),

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@ -102,6 +102,7 @@ class LiteEthUDPTX(Module):
self.comb += [
packetizer.sink.valid.eq(sink.valid),
packetizer.sink.last.eq(sink.last),
packetizer.sink.last_be.eq(sink.last_be),
sink.ready.eq(packetizer.sink.ready),
packetizer.sink.src_port.eq(sink.src_port),
packetizer.sink.dst_port.eq(sink.dst_port),