liteeth/core: handle last_be.
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@ -36,7 +36,9 @@ class LiteEthARPTX(Module):
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# # #
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counter = Signal(max=max(arp_header.length, eth_min_len), reset_less=True)
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packet_length = max(arp_header.length, eth_min_len)
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packet_words = packet_length//(dw//8)
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counter = Signal(max=packet_words, reset_less=True)
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self.submodules.packetizer = packetizer = LiteEthARPPacketizer(dw)
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@ -50,7 +52,8 @@ class LiteEthARPTX(Module):
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)
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)
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self.comb += [
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packetizer.sink.last.eq(counter == max(arp_header.length, eth_min_len)-1),
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packetizer.sink.last.eq(counter == (packet_words - 1)),
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packetizer.sink.last_be.eq(1 if len(packetizer.sink.last_be) == 1 else 2**(packet_length%(dw//8)-1)),
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packetizer.sink.hwtype.eq(arp_hwtype_ethernet),
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packetizer.sink.proto.eq(arp_proto_ip),
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packetizer.sink.hwsize.eq(6),
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@ -34,7 +34,8 @@ class LiteEthICMPTX(Module):
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packetizer.sink.code.eq(sink.code),
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packetizer.sink.checksum.eq(sink.checksum),
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packetizer.sink.quench.eq(sink.quench),
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packetizer.sink.data.eq(sink.data)
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packetizer.sink.data.eq(sink.data),
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packetizer.sink.last_be.eq(sink.last_be)
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]
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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@ -104,7 +105,8 @@ class LiteEthICMPRX(Module):
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source.ip_address.eq(sink.ip_address),
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source.length.eq(sink.length - icmp_header.length),
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source.data.eq(depacketizer.source.data),
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source.error.eq(depacketizer.source.error)
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source.error.eq(depacketizer.source.error),
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source.last_be.eq(depacketizer.source.last_be)
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]
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fsm.act("PRESENT",
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source.valid.eq(depacketizer.source.valid),
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@ -106,6 +106,7 @@ class LiteEthIPTX(Module):
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self.comb += [
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packetizer.sink.valid.eq(sink.valid & checksum.done),
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packetizer.sink.last.eq(sink.last),
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packetizer.sink.last_be.eq(sink.last_be),
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sink.ready.eq(packetizer.sink.ready & checksum.done),
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packetizer.sink.target_ip.eq(sink.ip_address),
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packetizer.sink.protocol.eq(sink.protocol),
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@ -231,7 +232,8 @@ class LiteEthIPRX(Module):
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source.protocol.eq(depacketizer.source.protocol),
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source.ip_address.eq(depacketizer.source.sender_ip),
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source.data.eq(depacketizer.source.data),
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source.error.eq(depacketizer.source.error)
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source.error.eq(depacketizer.source.error),
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source.last_be.eq(depacketizer.source.last_be)
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]
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fsm.act("PRESENT",
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source.valid.eq(depacketizer.source.valid),
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@ -102,6 +102,7 @@ class LiteEthUDPTX(Module):
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self.comb += [
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packetizer.sink.valid.eq(sink.valid),
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packetizer.sink.last.eq(sink.last),
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packetizer.sink.last_be.eq(sink.last_be),
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sink.ready.eq(packetizer.sink.ready),
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packetizer.sink.src_port.eq(sink.src_port),
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packetizer.sink.dst_port.eq(sink.dst_port),
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