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LiteEthMAC: remove logic loop in hybrid mode 

The hardware and cpu ports' valid signals can not be made dependent on
their own ready signals, since this creates combinatorial loops. This
should be unnecessary anyway though, the only thing that matters is that
the valid signal is not asserted while the other sink is not ready.
This commit is contained in:
Xiretza 2022-06-29 21:47:45 +02:00
parent 8ad6e2521c
commit 0f78f12651
1 changed files with 4 additions and 7 deletions
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11
liteeth/mac/__init__.py
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@ -84,7 +84,6 @@ class LiteEthMAC(Module, AutoCSR):
class LiteEthMACCoreCrossbar(Module): class LiteEthMACCoreCrossbar(Module):
def __init__(self, core, crossbar, interface, dw, hw_mac=None): def __init__(self, core, crossbar, interface, dw, hw_mac=None):
rx_ready = Signal() rx_ready = Signal()
rx_valid = Signal()
# IP core packet processing # IP core packet processing
self.submodules.packetizer = LiteEthMACPacketizer(dw) self.submodules.packetizer = LiteEthMACPacketizer(dw)
@ -123,23 +122,21 @@ class LiteEthMACCoreCrossbar(Module):
self.comb += [ self.comb += [
mac_match.eq(hw_mac == depacketizer.source.payload.target_mac), mac_match.eq(hw_mac == depacketizer.source.payload.target_mac),
rx_ready.eq(hw_fifo.sink.ready & (cpu_fifo.sink.ready | mac_match)), rx_ready.eq(hw_fifo.sink.ready & (cpu_fifo.sink.ready | mac_match)),
rx_valid.eq(rx_ready & depacketizer.source.valid),
depacketizer.source.connect(hw_fifo.sink, omit={"ready", "valid"}), depacketizer.source.connect(hw_fifo.sink, omit={"ready", "valid"}),
depacketizer.source.connect(cpu_fifo.sink, omit={"ready", "valid"}), depacketizer.source.connect(cpu_fifo.sink, omit={"ready", "valid"}),
depacketizer.source.ready.eq(rx_ready), depacketizer.source.ready.eq(rx_ready),
hw_fifo.sink.valid.eq(rx_valid), hw_fifo.sink.valid.eq(depacketizer.source.valid & (cpu_fifo.sink_ready | mac_match)),
cpu_fifo.sink.valid.eq(rx_valid & ~mac_match), cpu_fifo.sink.valid.eq(depacketizer.source.valid & hw_fifo.sink.ready & ~mac_match),
] ]
else: else:
# RX broadcast # RX broadcast
self.comb += [ self.comb += [
rx_ready.eq(interface.sink.ready & self.depacketizer.sink.ready), rx_ready.eq(interface.sink.ready & self.depacketizer.sink.ready),
rx_valid.eq(rx_ready & core.source.valid),
core.source.connect(interface.sink, omit={"ready", "valid"}), core.source.connect(interface.sink, omit={"ready", "valid"}),
core.source.connect(self.depacketizer.sink, omit={"ready", "valid"}), core.source.connect(self.depacketizer.sink, omit={"ready", "valid"}),
core.source.ready.eq(rx_ready), core.source.ready.eq(rx_ready),
interface.sink.valid.eq(rx_valid), interface.sink.valid.eq(core.source.valid & self.depacketizer.sink.ready),
self.depacketizer.sink.valid.eq(rx_valid), self.depacketizer.sink.valid.eq(core.source.valid & interface.sink.ready),
] ]
# TX arbiter # TX arbiter