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phy/gmii: add model parameter to skip clock buffers & generation 

To support a simple GMII simulation, skip clock generation and buffer
logic. This allows to operate a GMII interface over sys_clk. Proper
GMII clocking support can still be added in the simulation, this
should work when setting model = False.

It also sets an attribute "model" such that we can avoid adding
Platform constraints in the rest of the ecosystem (such as
litex/litex/soc/integration/soc.py, add_ethernet and add_etherbone).

Signed-off-by: Leon Schuermann <leon@is.currently.online>
This commit is contained in:
Leon Schuermann 2021-09-01 19:31:34 +02:00
parent c6c8be703b
commit 109002985a
1 changed files with 42 additions and 35 deletions
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13
liteeth/phy/gmii.py
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@ -47,7 +47,7 @@ class LiteEthPHYGMIIRX(Module):
class LiteEthPHYGMIICRG(Module, AutoCSR): class LiteEthPHYGMIICRG(Module, AutoCSR):
def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0): def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0, model=False):
self._reset = CSRStorage() self._reset = CSRStorage()
# # # # # #
@ -55,6 +55,7 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
self.clock_domains.cd_eth_rx = ClockDomain() self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain() self.clock_domains.cd_eth_tx = ClockDomain()
if not model:
# RX clock: GMII, MII Use PHY clock_pads.rx as eth_rx_clk. # RX clock: GMII, MII Use PHY clock_pads.rx as eth_rx_clk.
self.specials += Instance("BUFG", self.specials += Instance("BUFG",
i_I = clock_pads.rx, i_I = clock_pads.rx,
@ -90,14 +91,20 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
AsyncResetSynchronizer(self.cd_eth_tx, reset), AsyncResetSynchronizer(self.cd_eth_tx, reset),
AsyncResetSynchronizer(self.cd_eth_rx, reset), AsyncResetSynchronizer(self.cd_eth_rx, reset),
] ]
else:
self.comb += [
self.cd_eth_rx.clk.eq(ClockSignal()),
self.cd_eth_tx.clk.eq(ClockSignal()),
]
class LiteEthPHYGMII(Module, AutoCSR): class LiteEthPHYGMII(Module, AutoCSR):
dw = 8 dw = 8
tx_clk_freq = 125e6 tx_clk_freq = 125e6
rx_clk_freq = 125e6 rx_clk_freq = 125e6
def __init__(self, clock_pads, pads, with_hw_init_reset=True): def __init__(self, clock_pads, pads, with_hw_init_reset=True, model=False):
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset) self.model = model
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset, model=model)
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIITX(pads)) self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIITX(pads))
self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIRX(pads)) self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIRX(pads))
self.sink, self.source = self.tx.sink, self.rx.source self.sink, self.source = self.tx.sink, self.rx.source